tag: IEEE 1500

DRAM Test And Inspection Just Gets Tougher
By Anne Meixner - 07 Nov, 2023 - Comments: 0

DRAM manufacturers continue to demand cost-effective solutions for screening and process improvement amid growing concerns over defects and process variability, but meeting that demand is becoming much more difficult with the rollout of faster interfaces and multi-chip packages. DRAM plays a key role in a wide variety of electronic devices, from phones and PCs to ECUs in cars and servers ins... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part I
By Rahul Singhal - 11 Jan, 2022 - Comments: 0

The traditional processors designed for general-purpose applications struggle to meet the computing demands and power budgets of artificial intelligence (AI) or machine leaning (ML) applications. Several semiconductor design companies are now developing dedicated AI/ML accelerators that are optimized for specific workloads such that they deliver much higher processing capabilities with much low... » read more

Digital Test Bulks Up – Or Down
By Bryon Moyer - 08 Dec, 2020 - Comments: 2

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

STMicroelectronics’ Implementation Of The STAR Hierarchical System And IEEE 1500 Wrapping
By Synopsys - 01 Nov, 2017 - Comments: 0

This white paper discusses various IEEE 1500 architectures that STMicroelectronics has deployed using the Synopsys DesignWare STAR Hierarchical System test solution. STAR Hierarchical System allows users to optimize test time on system-on-chips that use multiple cores. The white paper provides guidelines on interface IP wrapping with IEEE 1500 to improve test time. In addition, it discusses the... » read more

Test Challenges Grow
By Mark LaPedus - 27 May, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our ... » read more

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