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Testing 2.5D And 3D-ICs


Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the ... » read more

Testing The Stack: DFT Is Ready For 3D Devices


When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II


By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Monitoring Chips After Manufacturing


New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Dealing With Test More Effectively


By Ed Sperling Shrinking geometries are starting to have the same effect on test as they are on other parts of an SoC, with the focus shifting from area to leakage, heat, noise, signal integrity, and the impact on overall system performance. The warning that design teams have to consider test much earlier in the design was issued to chipmakers years ago and largely ignored. At 28nm that war... » read more