tag: Imperas

RISC-V Processor Verification: Case Study
By Imperas - 22 Sep, 2021 - Comments: 0

Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an exp... » read more

Tradeoffs Between Edge Vs. Cloud
By Brian Bailey - 09 Sep, 2021 - Comments: 0

Increasing amounts of processing are being done on the edge, but how the balance will change between what's computed in the cloud versus the edge remains unclear. The answer may depend as much on the value of data and other commercial reasons as on technical limitations. The pendulum has been swinging between doing all processing in the cloud to doing increasing amounts of processing at the ... » read more

Modeling Chips From Atoms To Systems
By Ann Mutschler - 26 Aug, 2021 - Comments: 1

Complexity in hardware design is spilling over to other disciplines, including software, manufacturing, and new materials, creating issues for how to model more data at multiple abstraction levels. Challenges are growing around which abstraction level to use for a particular stage of the design, when to use it, and which data to include. Those decisions are becoming more difficult at each ne... » read more

Steering The Semiconductor Industry
By Brian Bailey - 26 Aug, 2021 - Comments: 2

Progress in semiconductors has been one of the most successful engineering feats, and the industry has ridden an exponential curve longer than anything else in history. It is also a highly conservative industry that has pushed away many disruptive changes in favor of small incremental changes that minimize risk. There have been significant changes over the decades, and they often required a ... » read more

Designing Chips In A ‘Lawless’ Industry
By Ed Sperling - 02 Aug, 2021 - Comments: 2

The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts. For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes wit... » read more

RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV
By Lee Moore - 29 Jul, 2021 - Comments: 1

By Lee Moore and Simon Davidmann The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating... » read more

Sweeping Changes Ahead For Systems Design
By Ann Mutschler - 29 Jul, 2021 - Comments: 0

Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources. Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible. But because there are so ma... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Jul, 2021 - Comments: 0

Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

Week In Review: Design, Low Power
By Jesse Allen - 02 Jul, 2021 - Comments: 0

Tools Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (st... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 02 Jul, 2021 - Comments: 0

Security The U.S. government agencies put out a warning that Russian military has been using a Kubernetes cluster to attempt distributed and anonymized brute force access against hundreds of government and private sector targets worldwide. Department of Homeland Security (DHS)’s Cybersecurity and Infrastructure Security Agency (CISA), the Federal Bureau of Investigation (FBI), the National S... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy