Slower Metal Bogs Down SoC Performance


Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

RISC-V: Will There Be Other Open-Source Cores?


Part 3: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

RISC-V’s Expanding Footprint


Zdenek Prikryl, CTO of Codasip, sat down with Semiconductor Engineering to talk about the RISC-V market, where this open instruction set architecture (ISA) is gaining ground, and what are the biggest challenges in working with this technology. SE: Where do you see the value in RISC-V? Is it for off-the-shelf processors or more customized components? Prikryl: A few years ago, RISC-V was us... » read more

A Sneak Peek Into SVE And VLA Programming


Download this white paper to get an overview of SVE, get information on the new registers and the new instructions, and learn about the Vector Length Agnostic (VLA) programming technique, including some examples. The Scalable Vector Extension (SVE) is an extension of the ARMv8-A A64 instruction set, recently announced by ARM. Following the announcement at Hot Chips 28, a few articles describ... » read more

RISC-V Markets, Security And Growth Prospects


Semiconductor Engineering sat down to discuss open instruction set hardware with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation.  Part one of this discussion is ... » read more

RISC-V Challenges And Opportunities


Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Open ISAs Gaining Traction


Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

Extending RISC-V ISA With Custom Instruction Set Extension


RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the application needs, without having to pay for area or power that will not be used. One of the groups is special; it has no predefined instruct... » read more