Executive Briefing: Wally Rhines

By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design, as part of its ongoing executive briefing series, sat down with Wally Rhines, Mentor Graphics' chairman and CEO, to talk about future problems, opportunities, and the gray areas that could go either way. What follows are excerpts of that conversation. SLD: Is the amount of time spent on verification increasing? Rhines: It depends on how you define who s... » read more

Surprises Abound As Subsystem IP Gains Prominence

By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

Inside The System-Level Supply Chain

By Ed Sperling - 31 Jan, 2013 - Comments: 0

System-Level Design sat down to discuss supply chain issues with Bill Chown product marketing director for the system-level engineering division at Mentor Graphics and a longtime participant in a number of standards efforts across the semiconductor design industry. What follows are excerpts of that conversation. SLD: What’s happening with system engineering as chip design/manufacturing mo... » read more

12 Design Techniques For Successful Integration Of Data Converter IP Into An SoC

By Various Writers - 19 Dec, 2012 - Comments: 0

To deliver the demanding performance and faster operation of today’s systems—from communication interfaces to high-image-quality video and multimedia systems—consumer applications employ digital signal processing extensively. Data converters form the interface between the real-world analog signals and the digital domain. They are, therefore, an essential element of the complete signal pro... » read more

Experts At The Table: IP Integration Hurdles

By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversatio... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: integration

Executive Briefing: Wally Rhines

Surprises Abound As Subsystem IP Gains Prominence

Inside The System-Level Supply Chain

12 Design Techniques For Successful Integration Of Data Converter IP Into An SoC

Experts At The Table: IP Integration Hurdles