Chip Industry’s Technical Paper Roundup: Oct 18

New technical papers added to Semiconductor Engineering’s library this week. [table id=57 /] » read more

Accelerating Off-Chip Load Requests By Removing The On-Chip Cache Access Latency From Their Critical Path

A new technical paper titled "Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction" was published by researchers at ETH Zurich, Intel Processor Architecture Research Lab, and LIRMM, Univ. Montpellier, CNRS.  The work received a best paper award at MICRO 2022. Abstract "Long-latency load requests continue to limit the performance of high-performance ... » read more