Week In Review: Design, Low Power


Arm and Intel Foundry Services inked a multi-generation agreement to enable chip designers to build Arm-based SoCs on the Intel 18A process. The initial focus is mobile SoC designs, but the deal allows for potential expansion into automotive, IoT, data center, aerospace, and government applications. IFS and Arm will undertake design technology co-optimization (DTCO) to optimize chip design and ... » read more

RISC-V Driving New Verification Concepts


Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

Chiplet Security Risks Underestimated


The semiconductor ecosystem is abuzz with the promise of chiplets, but there is far less attention being paid to security in those chiplets or the heterogeneous systems into which they will be integrated. Disaggregating SoCs into chiplets significantly alters the cybersecurity threat landscape. Unlike a monolithic multi-function chip, which usually is manufactured using the same process tech... » read more

Week In Review: Semiconductor Manufacturing, Test


The U.S. Commerce Department outlined proposed rules for the Chips for America Incentives Program, including additional details on national security measures applicable to the CHIPS Incentives Program included in the CHIPS and Science Act. The rules limit funding recipients from investing in the expansion of semiconductor manufacturing in foreign countries of concern, notably the People’s Rep... » read more

Week In Review: Design, Low Power


Synopsys rolled out an AI-driven design suite called Synopsys.ai at the Synopsys User Group conference this week, which it says reduces time to better results at multiple points in the design flow. The company noted the new technology uses reinforcement learning, which compensates for relatively small data sets by allowing engineers to interact with that data more easily at any point, and to ch... » read more

Do Necessary Tools Exist For RISC-V Verification?


Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, senior director of alliances partner... » read more

Week In Review: Manufacturing, Test


TEL announced plans to build a ¥2.2 billion ($168.2 million) production and logistics center at its Tohoku Office to increase capacity. Construction of the 57,000m² facility, which will be used for manufacturing thermal processing and single-wafer deposition systems, is slated to start in spring 2024, and expected to be completed in fall 2025. Toshiba's board voted in favor of a 2 trillio... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Ford expects to lose $3 billion from EV sales this year, but said that part of the business will begin generating profits soon. The company still expects to hit its overall profit numbers for the year, however. Volvo is making a new electric vehicle (EV) in China and exporting it to Europe and Japan, according to a Nikkei Asia interview. Volvo is owned by Zhejiang Geely... » read more

The Race Toward Mixed-Foundry Chiplets


Creating chiplets with as much flexibility as possible has captured the imagination of the semiconductor ecosystem, but how heterogeneous integration of chiplets from different foundries will play out remains unclear. Many companies in the semiconductor ecosystem are still figuring out how they will fit into this heterogeneous chiplet world and what issues they will need to solve. While near... » read more

Big Changes Ahead In Power Delivery, Materials, And Interconnects


Part one of this forecast looked at evolving transistor architectures and lithography platforms. This report examines revolutions in interconnects and packaging. When it comes to device interconnects, it’s hard to beat copper. Its low resistivity and high reliability have served the industry exceedingly well as both on-chip interconnect and wires between chips. But in logic chips, with int... » read more

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