Week In Review: Semiconductor Manufacturing, Test

NTSC names board-selection committee; Intel unbundles fab; Lam adds virtual process unit, X-FAB runs EU photonics effort; sustainable startups.


The CHIPS for America team at the U.S. Department of Commerce named the selection committee who will select board members for the nonprofit entity that will likely be managing the National Semiconductor Technology Center (NSTC). Members include John Hennessy, chairman of Alphabet; Jason Matheny, president and CEO of the RAND Corporation; Don Rosenberg, fellow in residence at UCSD’s School of Global Policy and Strategy; Brenda Wilkerson, president and CEO of nonprofit AnitaB.org; and Janet Foutty, a principal at Deloitte Consulting.

During India’s state visit to the United States this week, the U.S. President Biden and India’s Prime Minister Modi solidified the two countries’ agreements to work together on semiconductor technology in a Fact Sheet and Joint Statement.

Lam Research rolled out a new physical-virtual ecosystem it calls Semiverse Solutions. The business unit will focus on solutions and services to enable virtual fabrication and will be headed by David Fried, corporate vice president. The focus includes advanced plasma, fluid, electromagnetic, and particle simulations that can be used to refine processes quicker using fewer materials. The company also plans to educate up to 60,000 Indian engineers in nanotechnologies over the next 10 years to help combat the industry’s ongoing talent shortage.

Lam Research also introduced the Coronus DX, a wafer edge CVD system that was developed in collaboration with CEA-Leti for 3D NAND, wafer bonding and advanced logic applications. The tool builds on technologies from the Coronus bevel etch tool including precision wafer centering capability and plasma shaping using edge rings. Designed to passivate edge damage from repeated cleaning cycles and copper CMP run-off, yield improvement of 0.2-0.5% per layer is expected.

Micron Technology will open a new DRAM and NAND assembly and test facility in Gujarat, India.

Applied Materials will establish a collaborative engineering center in Bangalore, India for developing semiconductor manufacturing equipment. The center will cost $400 million.

Intel will build two fabs in Magdeburg, Germany, that will manufacture advanced chips, on a site dubbed “Silicon Junction.” The company and the German government signed a revised letter of intent to build a leading-edge wafer fabrication, in which Intel will invest 30 billion euros along with the EU incentives. The fabs will go live in four to five years.

Intel is updating its internal foundry model. Internal product groups will function more like a fabless semiconductor company and have a “foundry-style relationship” with the manufacturing side of the house. Beginning in Q1 2024, the manufacturing group will be responsible for its own profit and loss and will have to compete with other foundries. The in-house design teams will become Client Computing, Data Center and AI, Network and Edge, and All Other groups, and will have to pay market-based pricing to its internal business units. The product groups will “have the flexibility over time to engage with third-party foundries,” according to Intel’s press release. Intel expects to save the company $8 billion to $10 billion by 2026.

The U.S. Department of Commerce’s National Institute of Standards and Technology (NIST) has a new public working group on artificial intelligence (AI). The Public Working Group on Generative AI will look into the opportunities and challenges for generative AI. The group will collect the input on guidance — also known as a profile — for NIST ‘s AI Risk Management Framework (AI RMF).

SEMI announced finalists in its second annual Startups for Sustainable Semiconductors. This year the focus was innovative technologies for circularity (water and waste), emissions, and energy efficiency. The finalists in circularity are ElectraMet for strategic metal recovery from process water and wastewater streams; GRAPHEC for low-cost electrode material for electrochemical water treatment without oxidizing chloride; and Purity ReSource for recovery of chemical resources. Emissions finalists are CFEX for a tracking system of Scope 2 emissions across supply chains; InnoFlex for scalable rooftop photocatalytic systems to break down F-GHGs and other greenhouse gases; and Multiscale Technologies for software that helps teams speed up their search for improvements in materials and manufacturing processes. Energy finalists are Aqua Membranes for elements using printed spacers compatible with existing systems to reduce wasted energy by up to 60% and increase rates of water reuse and recycling; Corintis for silicon microfluidic cooling; and L2X Labs’ for its work on EUV technology for chip manufacturing.

X-FAB will lead an EU-funded photonics consortium, the photonixFAB, which is working on growing European silicon photonics supply chain. One of the goals is to create low-barrier access to low-loss silicon nitride (SiN) and silicon-on-insulator (SOI) -based photonics platforms with indium phosphide (InP) and lithium niobate (LNO) heterogenous integration capabilities.  The consortium is overseeing six demonstrator projects that are building different types of electronics devices to validate the photonics value chains. The members in photonixFAB are EU research institutes and companies, with funding support from the Key Digital Technologies Joint Undertaking (KDT JU), and the EU and national entities.

How far can a RISC-V design be pushed and still be compliant? The answer isn’t black-and-white because RISC-V is a new type of open source. Constructive discussions are taking place to address some of the challenges of designing with an open-standard ISA, as this special report shows.


Keysight’s signal generators, analyzers, and wireless test sets are now validated to verify new chipset designs for Open RAN radio units on Qualcomm Development Acceleration Resource Toolkit (QDART).

DB GlobalChip is using Cadence’s Spectre FX Simulator, with its Spectre AMS Designer, to verify GlobalChip’s analog and mixed-signal IP.

Codasip selected SmartDV Technologies as its preferred provider of peripheral design IP. Customers of Codasip can now license some of SmartDV’s peripheral IP under a single license agreement and contract.

Advantest and NXP are working with Arizona State University (ASU) on a new test engineering curriculum that started off as a class. The curriculum, called “EEE 522 Radio Frequency Test,” was created by ASU, with Advantest adding in laboratory experiments that were administered jointly by Advantest and NXP during the 2023 spring semester. The course will be offered each semester going forward.


Expedera opened design centers in Taipei and Shanghai to and a Chinese language website.

Intel will sell its 20% stake in its IMS Nanofabrication GmbH (IMS) business to Bain Capital in a transaction expected to close in Q3 2023.  The transaction values at approximately $4.3 billion. IMS will operate as a standalone subsidiary led by CEO Elmar Platzgummer.

Ansys is opening an office in Kigali, Rwanda, to serve its customers in the Kigali Innovation City. The company will also partner with Carnegie Mellon University (CMU) to provide advanced engineering talent from CMU-Africa, which has an engineering school in Kigali.

Further reading 

See more Semiconductor Engineering top stories.


  • Keysight World, June 20 – 23
  • Leti Innovation Days, June 27 – 29
  • Samsung Foundry Forum & SAFE Forum 2023, San Jose, Calif., June 27 – 28
  • SEMICON China, June 29 – July 1
  • MIPI DevCon 2023, San Jose, Calif., June 30
  • DAC 2023, San Francisco, Calif., July 9 – 13
  • SEMICON West 2023, San Francisco, Calif., July 11 – 13
  • Rambus Design Summit, July 18 – 19

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