One-On-One: Dave Hemker

By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Dave Hemker, senior vice president and chief technology officer at [getentity id="22820" comment="LAM Research"]. SE: On the technology front, the IC industry is undergoing some new and dramatic changes. What are some of those changes? Hemker: We focus on what we call the inflections.... » read more

Designing For Security

By Ernest Worthman - 08 Jan, 2015 - Comments: 0

Stacked die may improve performance and lower power, but the use of [getkc id="203" kc_name="through-silicon vias"] (TSVs) could add new security risks. As IC structures go, the vertical component of these chip packages is both a boon and a bust. Three-dimensional geometries allow for much less complexity in design by stacking two-dimensional dies and interconnecting them in the third dimens... » read more

2.5D Timetable Coming Into Focus

By Ed Sperling - 23 Oct, 2014 - Comments: 0

After years of empty promises, the timetable for [getkc id="82" kc_name="2.5D"] is coming into better focus. Large and midsize chipmakers are behind it, real silicon is being developed, and contracts are being signed. That doesn't mean all of the pieces are in place or that market uptake is at the neck of the hockey stick. And it certainly doesn't mean the semiconductor industry is going to ... » read more

Multi-Die Packaging Gains Steam

By Si2 - 06 Oct, 2014 - Comments: 0

By Herb Reiter Many readers will be familiar with my extensive background and focus in the emerging field of 3D IC technology, including both 3D stacked die and 2.5 interposer design flows. Now, I am excited to bring my expertise and passion to Silicon Integration Initiative (Si2), where I am now Director of 3D Programs, helping Si2’s members in the Open3D Technical Advisory Board develop pr... » read more

When Will 2.5D Cut Costs?

By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Time To Revisit 2.5D And 3D

By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

Where Is 2.5D?

By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

MEMS Foundries Play Waiting Game

By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus For years, the foundries in the microelectromechanical systems (MEMS) business have been patiently waiting for the MEMS integrated device manufacturers (IDMs) to outsource some or all of their production. The MEMS foundries are still waiting for that development. Because MEMS are custom devices tuned to a proprietary process and toolset, IDMs still prefer to use their own f... » read more

Marching Orders

By Ed Sperling - 20 Jun, 2013 - Comments: 0

Reports back from the front lines of Moore’s Law are rather consistent—14nm and 16nm finFETs are do-able, but they’re not easy to design, verify or manufacture. In fact, the only high-volume source of production-proven finFETs at this point is Intel, which is turning them out at 22nm. A number of issues are cropping up at the most advanced nodes, and while each is ultimately solvable, ... » read more

Stacked Die From A Networking Angle

By Mark LaPedus - 24 Jan, 2013 - Comments: 1

By Mark LaPedus The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments. Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are sepa... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: interposers