1xnm DRAM Challenges

By Mark LaPedus - 18 Feb, 2016 - Comments: 3

At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

Predictions For 2016: Semiconductors, Manufacturing And Design

By Brian Bailey - 21 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Taming Mask Metrology

By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

Mask Metrology Challenges Grow

By Mark LaPedus - 29 Sep, 2015 - Comments: 0

Photomasks are becoming more complex at each node. In fact, masks are moving from traditional shapes to non-orthogonal patterns and complex shapes, such as curvilinear mask patterns. To measure patterns and shapes on the mask, photomask makers use traditional critical-dimension scanning electron microscopes (CD-SEMs). In general, the CD-SEM, the workhorse metrology tool in the mask shop, use... » read more

Tech Talk: Inverse Lithography

By Ed Sperling - 11 Dec, 2014 - Comments: 0

D2S’ Leo Pang talks with Semiconductor Engineering about lithography, inverse lithography, photomasks, where the problems are, and what needs to be done to move forward. [youtube vid=mn8JWaP8Z68] » read more

One-On-One: Linyong Pang

By Mark LaPedus - 12 May, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss trends in the lithography and photomask business with Linyong “Leo” Pang, the new chief product officer and executive vice president at D2S, which focuses on model-based mask data preparation as well as other mask writing technologies. What follows are excerpts of that conversation. SE: Before you arrived at D2S you were at Luminescent, whic... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer