Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

The Rise Of Layout-Dependent Effects

By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

SoC Architects Face Big Challenges

By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Power Impacts On Advanced Node IP

By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler With the move to the 28nm or 20nm process nodes, SoC engineering teams are seeing a significant amount of variations due to manufacturability. To reflect how a design element will be printed on the wafer, foundries offer many libraries with multiple corners for different voltages, timing and temperature, among other things. “At 28nm what we are seeing is a l... » read more

Experts at the Table: Black Belt Power Management

By Ann Mutschler - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss rising integration challenges caused by an increasing amount of black-box IP with Qi Wang, technical marketing group director, solutions marketing, for the low-power and mixed-signal group at Cadence; J. Bhasker, architect at eSilicon Corp.; Navraj Nandra, senior director of product marketing for analog an... » read more

Reducing Circuitry To Reduce Power

By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

Experts At The Table: Black Belt Power Management

By Ann Mutschler - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification. Integration challenges continue to mount with the increasing amount of black ... » read more

Connecting IP Blocks

By Ann Mutschler - 07 Oct, 2010 - Comments: 0

Is there a standard way to hook up specifically low-power IP blocks today? For all intents and purposes, no. Before even talking about IP interoperability in terms of power, Philippe Magarshack, general manager of central CAD and design solutions at STMicroelectronics asserted those IPs must be hooked up correctly functionally and in a productive and safe way. He said ST is forging ahead ... » read more

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Knowledge Centers
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tag: IP integration