Experts At The Table: Black Belt Power Management

First of three parts: With 80% of SoC content re-used from past designs or brought in from internal and external IP sources, the engineering team is tasked with writing glue logic and verification of the integrated pieces.


By Ann Steffora Mutschler

With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification.

Integration challenges continue to mount with the increasing amount of black box IP and subsystems. What is the best way to approach integration, and how is power managed in a black box?

“Definitely there’s a challenge how to first model them,” noted Qi Wang, technical marketing group director for solutions marketing in Cadence’s low power and mixed signal group. He pointed out that there’s a misunderstanding that if it’s truly a black box, there’s nothing to model, but that’s not true. “The system is getting more and more complicated—there’s a need to model those so-called black boxes, power features, timing features, implementation features.”

Then these black boxes must be integrated and annotated. Finally, they must be put into the system and verified to make sure they operate in the way the specification calls for.

“You get a black box—it’s not like a brick—it has some functionality that you need to put in the whole system to run the verification. The whole system verification in that sense, nothing is a black box and you have to verify with your system functional spec,” Wang explained. It’s all about IP modeling, SoC integration and SoC verification.

J. Bhasker, architect at eSilicon, said a significant challenge in integrating black-box IP is how much, or how little, information is available to the IP user. “Sometimes all you get is the list of IP that says in order to switch out this power, you have to switch out this other power and this function is off. But the question is how much information is provided in terms of black box. You need to know the functionality you are turning off and on. It’s not enough to say power goes off on this island, power goes off on this island. You really need to know the functionality that goes with it. To me, it’s important that the set of documentation or information provided to help understand what part of the black box is affected by what power.”

When it comes to the physical integration side, this can be even more challenging as it concerns power delivery. “You have a black box. You don’t know what’s inside. Now you have to figure out how you’re going to deliver. Maybe it has five different power domains. Maybe it needs to have five different sub-power supplies. Does the black box have to sit in the corner of the chip? Can it sit in the middle of the chip? These are all important decisions that you’re going to have to make as you’re designing the chip,” he continued.

What this all boils down to is that the integrator (SoC developer) needs to understand how to hook up the black box or the IP block into the rest of the SoC, asserted Navraj Nandra, senior director of product marketing for analog and mixed signal IP in the solutions group at Synopsys.

“What we’re seeing is there are multiple black boxes on an SoC now and they come from multiple sources sometimes. They all need to talk in some kind of language that’s common so that these things can interface and interact with each other. When we get into some of the more interesting aspects, which are things like power consumption, there needs to be some ability for the items in the black box to be able to get into low power states. But some of this is actually not controlled by the black boxes. It comes from above at the system level,” he observed.

What’s very interesting from an integration and design perspective is that all of these things are happening simultaneously, concurrently and asynchronously. “You can’t think anymore in terms of sequences of logic,” Nandra said. “You have to think sometimes asynchronously. The asynchronization of the power management needs to be done at the verification stage and also controls the SoC integration part as well. And it takes many, many people to do this in the development stage. You can’t just have one person that understands that flow like years ago when you had a low power architect. Now you have multiple low power architects. You’ve got to manage all of that through some kind of infrastructure.”

Stepping back a few steps, Peter Suaris, senior director of engineering at Atrenta, added that the choice of modules is important as well. “The key there is to be able to estimate very early what your modules are doing, what the integration power is, and based on that make the right tradeoffs. Also, when you design the module independently you don’t really see how it is integrated with the rest of world. There are many opportunities to turn off power because a lot of the signal’s activity actually depends on how it is used. There are a lot of opportunities that you haven’t thought about at the lower level that present themselves when you integrate.”

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