tag: IP reuse

Bridging Hardware And Software
By Ann Mutschler - 18 Jan, 2016 - Comments: 1

Methodology and reuse are two fairly standard concepts when it comes to semiconductor design, but they're viewed completely differently by hardware and software teams. It's a given that hardware and software have different goals and opinions about how best to do design. And while all agree that a single methodology can pay dividends in future chips, there is disagreement over who should shap... » read more

The Beginning
By Anupam Bakshi - 22 Dec, 2015 - Comments: 0

We all want our creations to transcend time. Our products, our designs—even our specifications. Specifications are more than just ideas or collections of requirements or static collections of implementation details. They live inside many chips and many designs, and the more flexible and portable they are, the longer they remain relevant. End devices may be replaced relatively quickly, but ... » read more

A New Reuse Paradigm To Take 2.5D Packaging Technology Mainstream
By Jeff Scott - 23 Oct, 2014 - Comments: 0

With all of the recent product implementations and demonstrations of the technical viability of 2.5D technology, there is a lot of excitement around its potential. However, as with any new technology, there are concerns with cost and risk that limit mainstream adoption. Cost reduction and risk mitigation require some level of volume production, and therein lies a classic Catch-22. Is there a wa... » read more

Platforms, Standards, Methodologies Conquer Design Challenges
By Brian Fuller - 10 Apr, 2014 - Comments: 0

We in the electronics design world always have spent a lot of time wringing our hands (will we ever get to design below 1 micron??) And while the problems are not imagined—they’re often soberingly real—we tend to plow through them, or, when necessary around them. Today, amid increasing complexity and risk, we’re leveraging platforms, standards and new methodologies to slay these d... » read more

2014 Accellera Standards Are Built on Powerful Shoulders
By Accellera - 27 Jan, 2014 - Comments: 0

By Adam Sherer Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon whic... » read more

Uncertainty Increases About What’s Next
By Ed Sperling - 24 Oct, 2013 - Comments: 0

Across the semiconductor industry, there is a lot of talk about what’s next. Lithography advances have stalled, NRE and mask costs are rising, and complexity is exploding. But unlike the 1 micron wall, which was supposed to be impenetrable, there is no single issue holding back progress. Instead, there are lots of them, most with pricey workarounds, but which together become more complicat... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Pitfalls In Subsystem Reuse
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Reducing Circuitry To Reduce Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

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