tag: IP

Why I See C In SCE-MI
By Jacek Majkowski - 24 Mar, 2016 - Comments: 0

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs
By NetSpeed Systems - 23 Mar, 2016 - Comments: 0

The last few decades have seen a massive growth in the number of CPU cores, computing clusters and other IP blocks in a SoC. This massive growth along with the need for complex chip integration has driven the need for sophisticated interconnects. SoC architects have employed a variety of methods from buses to crossbars to handcrafted NoCs with Lego-like blocks with varying degrees of success. T... » read more

What’s Next for System-Level Power Modeling?
By Alan Gibbons - 23 Mar, 2016 - Comments: 1

Availability of models and libraries has long been one of the biggest barriers to the adoption of new EDA tools and methodologies, whether due to the investment needed to create these models and libraries or because of the “at-risk” nature of developing complex models in proprietary formats. With the approval of UPF3.0 (IEEE 1801-2015) this past December, we now have an industry standar... » read more

IP Risk Sharing
By Brian Bailey - 10 Mar, 2016 - Comments: 0

For most people within the semiconductor industry, managing risk involves making the right product decisions that will enable a company to be profitable, and ensuring the product is successfully produced within the necessary time window. In contrast, for products within high-risk areas such as medical and mil/aero, design often proceeds at a slower pace, using proven technologies and adopting l... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

The Price Of Fear
By Ed Sperling - 03 Mar, 2016 - Comments: 0

Fear sells, and judging from the attendance numbers and the messages coming out of this week's RSA Conference, it's selling quite well. Increasing connectedness comes at a significant price, and apparently lots of people are willing to pay that price. Security has become a huge and growing business. Attendance is one indicator. There were an estimated 40,000 attendees at this year's conferen... » read more

Back Doors Are Everywhere
By Ernest Worthman - 03 Mar, 2016 - Comments: 0

By Ernest Worthman & Ed Sperling Back doors have been a part of chip design since the beginning. One of the first open references was in the 1983 movie "War Games," which features a young computer whiz who uses one to hack into a computer that controls the United States' nuclear arsenal. In reality, modern back doors predate Hollywood's discovery by about 20 years, starting in 1965 wi... » read more

IP Requirements Changing
By Brian Bailey - 25 Feb, 2016 - Comments: 0

Twenty years ago the electronics industry became interested in the notion of formalizing re-use through third-party IP. It has turned out to be harder than anyone imagined. In 1996, the Virtual Socket Interface Alliance ([getentity id="22845" comment="VSIA"]) was formed to standardize the development, distribution and licensing of IP. Soon afterward, companies with a couple of people in a ga... » read more

An Architecture Synthesis Platform For Rapidly Evolving SoC Designs
By NetSpeed Systems - 24 Feb, 2016 - Comments: 0

Modern System-on-Chip (SoC) architects are faced with a number of serious challenges. First, the number of Semiconductor Intellectual Property (IP) blocks in SoC designs is growing continuously and increasing design complexity. With IP design reuse becoming more common, the mixing and matching of IP components is further compounding design complexity. Second, sophisticated SoC applications are ... » read more

The Big Shift
By Ed Sperling - 18 Feb, 2016 - Comments: 0

The number of chipmakers that truly can differentiate their products by moving to the next process node is falling, and that pool will continue to shrink even further over the next few years. Processor companies such as Intel and IBM always will benefit from scaling and architectural changes. So will GPU companies such as Nvidia, and FPGA vendors such as Xilinx, Microsemi and Altera (now par... » read more

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