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Getting Formal With Power


By Ed Sperling Formal methodologies have always been an important tool in the verification engineer’s toolbox because they often can pinpoint bugs faster and with more accuracy than other verification approaches. The problem is that most engineers don’t know how to use them, and understanding this technology to a proficiency level requires a learning curve that most engineers consider pain... » read more

Remaking The Design Landscape


By Ed Sperling Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transa... » read more

Formal Verification 101


By Clive "Max" Maxfield The first time I came into contact with the concepts of a digital hardware description language (HDL) and digital logic simulation, I inherently understood how it all "worked." The idea that the statements in the modeling language acted in a concurrent manner just seemed to make sense. By comparison, trying to wrap my brain around formal verification has always mad... » read more

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