Making Chips Yield Faster At Leading-Edge Nodes


Simulation for semiconductor manufacturing is heating up, particularly at the most advanced nodes where data needs to be analyzed in the context of factors such as variation and defectivity rates. Semiconductor Engineering sat down with David Fried, corporate vice president of computational products at Lam Research, to talk about what's behind Lam's recent acquisition of Esgee Technologies, ... » read more

Week In Review: Semiconductor Manufacturing, Test


Chinese memory chip maker YMTC and dozens of other Chinese entities are "at risk" of being added to a trade blacklist as soon as Dec. 6, a U.S. Commerce Department official said in prepared remarks seen by Reuters. SMIC co-CEO Zhao Haijun said on an earnings call that recent export controls from the United States will have an "adverse impact" on the company's production. The U.K. has rule... » read more

Challenges In Backside Power Delivery


One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions. Backside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on t... » read more

Creating Airgaps To Reduce Parasitic Capacitance In FEOL


Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the effective dielectric constant of the material layers between the gate and source/drain. This can be done by creating airgaps in the dielectric material at that location. This type of work has been do... » read more

Where All The Semiconductor Investments Are Going


Companies and countries are funneling huge sums of money into semiconductor manufacturing, materials, and research — at least a half-trillion dollars over the next decade, and maybe much more — to guarantee a steady supply of chips and know-how to support growth across a wide swath of increasingly data-centric industries. The build-out of a duplicate supply chain that can guarantee capac... » read more

Blog Review: Nov. 16


Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

Blog Review: Nov. 9


Cadence's Claire Ying finds that the latest update to CXL, which introduced memory-centric fabric architectures and expanded capabilities for improving scale and optimizing resource utilization, could change how some of the world’s largest data centers and fastest supercomputers are built. Synopsys' Gervais Fong and Morten Christiansen examine the latest updates in the USB 80Gbps specifica... » read more

Legacy Tools, New Tricks: Optical 3D Inspection


Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; Various struc... » read more

Week In Review: Semiconductor Manufacturing, Test


Nikkei Asia reports the U.S. is urging allies, including Japan, to restrict exports of advanced semiconductors and related technology to China. The U.S. holds 12% of the global semiconductor market, Japan has a 15% share, while Taiwan and South Korea each have about a 20% share. Some U.S. companies have called for other countries to adopt U.S.-style export curbs, arguing it is unfair for only A... » read more

Chip Industry Earnings: A Mixed Bag


Editor's Note: Updated the week of Oct. 31 and Nov. 7 for additional earnings releases. Although most companies reported revenue growth, this latest round of chip industry earnings releases reflected a few major themes: Lower future quarter guidance to varying degrees, due to the recent U.S. export restrictions related to China; Negative impact of the inflationary environment on corn... » read more

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