Searching For Power Bugs


How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Four Steps For Static Verification Of Low Power Designs Using UPF With VC LP


Low power consumption has always been a key requirement for portable electrical and electronic devices. In recent years, this requirement has been extended to many more categories of end products. The electronics industry has developed a wide range of techniques for power management and has defined the Unified Power Format (UPF) to describe design intent for some of the most common methods. Suc... » read more

Taming Concurrency


Concurrency adds complexity for which the industry lacks appropriate tools, and the problem has grown to the point where errors can creep into designs with no easy or consistent way to detect them. In the past, when chips were essentially a single pipeline, this wasn't a problem. In fact, the early pioneers of EDA created a suitable language to describe and contain the necessary concurrency ... » read more

Automation Can’t Replace Human Intervention


We work in a dynamic industry where the focus is on making it easier to design and verify semiconductor chips by automating tasks for the design engineer. There is so much emphasis on this that I wonder if it is easy to forget the value of that designer’s experience. No matter how automated a process gets, there is always the fundamental assumption that the engineer knows what is happening be... » read more