tag: low-power design

Modeling On-Chip Variation At 10/7nm
By Ann Mutschler - 14 Jun, 2017 - Comments: 1

Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

Saving Power In A UFS Implementation Leveraging MIPI M-PHY And UniPro
By Synopsys - 07 Jun, 2017 - Comments: 0

The JEDEC Universal Flash Storage (UFS) has become the mobile storage standard of choice for today’s high-end smartphones and tablets mainly due to the specification’s performance and power advantages over other existing solutions. These advantages become critical to meet end users’ requirements for higher responsiveness and increased capabilities. For example, end users expect to transmi... » read more

Moore’s Law: Toward SW-Defined Hardware
By Ed Sperling - 15 May, 2017 - Comments: 2

Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

The Future Of Sports Cars
By Ed Sperling - 11 May, 2017 - Comments: 1

The introduction of autonomous vehicles will have a huge effect on the car market, but not for the obvious reasons—and not necessarily in the time frame that most people expect. Numerous sources say one automakers are very concerned about what kinds of vehicles people will buy once cars are autonomous. What will differentiate one car from another? And what will become of brands such as Por... » read more

Power Just One Piece Of The Puzzle At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 0

With dynamic power density and rising leakage power becoming more problematic at each new node, it is more important than ever to look at designs today with power in mind from the very start. As part of this complex picture of electronic design today, every piece in the design flow must tie together for the greatest efficiency and optimization. While this is partly power, there are more... » read more

Closing The Loop On Power Optimization
By Brian Bailey - 11 May, 2017 - Comments: 2

[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Tech Talk: eFPGA Acceleration
By Ed Sperling - 03 May, 2017 - Comments: 0

Achronix's Kent Orthner talks about when and why to use embedded FPGAs, and how they co-exist with—and compare to—other processing elements. [youtube vid=TXeIOmo7O9o] » read more

The Problem With Clocks
By Brian Bailey - 13 Apr, 2017 - Comments: 1

The synchronous digital design paradigm has enabled us to design circuits that are well controlled, but that is only true if the clocks themselves are well controlled. While overdesign techniques ensured that to be the case in early ASIC development, designs today cannot afford such luxuries. As we strive for lower power and higher operating frequencies, the clock has become a critical desig... » read more

Managing Voltage Drop At 10/7nm
By Ann Mutschler - 13 Apr, 2017 - Comments: 0

Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Intelligent Power Allocation
By Arm - 12 Apr, 2017 - Comments: 0

The modern System-on-Chip (SoC) has higher thermal dissipation than its previous generations, because of the following factors: Increasing processor frequencies. Decreasing SoC package and device sizes. Higher levels of integration. Static power consumption trends with the most advanced SoC fabrication[1]. Faster frequencies mean faster switching, which means more power consumption... » read more

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