tag: low-power design

Power Just One Piece Of The Puzzle At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 0

With dynamic power density and rising leakage power becoming more problematic at each new node, it is more important than ever to look at designs today with power in mind from the very start. As part of this complex picture of electronic design today, every piece in the design flow must tie together for the greatest efficiency and optimization. While this is partly power, there are more... » read more

Closing The Loop On Power Optimization
By Brian Bailey - 11 May, 2017 - Comments: 2

[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Tech Talk: eFPGA Acceleration
By Ed Sperling - 03 May, 2017 - Comments: 0

Achronix's Kent Orthner talks about when and why to use embedded FPGAs, and how they co-exist with—and compare to—other processing elements. [youtube vid=TXeIOmo7O9o] » read more

The Problem With Clocks
By Brian Bailey - 13 Apr, 2017 - Comments: 1

The synchronous digital design paradigm has enabled us to design circuits that are well controlled, but that is only true if the clocks themselves are well controlled. While overdesign techniques ensured that to be the case in early ASIC development, designs today cannot afford such luxuries. As we strive for lower power and higher operating frequencies, the clock has become a critical desig... » read more

Managing Voltage Drop At 10/7nm
By Ann Mutschler - 13 Apr, 2017 - Comments: 0

Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Intelligent Power Allocation
By Arm - 12 Apr, 2017 - Comments: 0

The modern System-on-Chip (SoC) has higher thermal dissipation than its previous generations, because of the following factors: Increasing processor frequencies. Decreasing SoC package and device sizes. Higher levels of integration. Static power consumption trends with the most advanced SoC fabrication[1]. Faster frequencies mean faster switching, which means more power consumption... » read more

Pushing Batteries Too Far?
By Ed Sperling - 06 Apr, 2017 - Comments: 0

Reports of battery fires in consumer devices are not abating. The culprit in almost all cases is the lithium-ion battery. In some cases, this is a manufacturing issue, where predictable intervals of failure can point to a breach in the membrane separating the anode and cathode or a metal particle contaminant that causes a short circuit. Those kinds of flaws are well understood, based upon ho... » read more

Self-Driving Cars Rattle Supply Chain
By Ann Mutschler - 06 Apr, 2017 - Comments: 0

Automotive compute workloads are consolidating as carmakers push toward autonomous vehicles, but the changes necessary to make this all work are causing huge disruptions in an industry that has fine-tuned its supply chain over more than a century. Consolidation is essential for a variety of reasons, including efficiency of the computations, complexity management, and lower deployment costs. ... » read more

HBM Upstages DDR In Bandwidth, Power
By Ann Mutschler - 30 Mar, 2017 - Comments: 1

For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

TFETs And/Or MOSFETs For Low-Power Design
By Katherine Derbyshire - 16 Mar, 2017 - Comments: 0

As discussed in Reducing Subthreshold Swing With TFETs, papers at December’s IEEE Electron Device Meeting examined a variety of potential designs for tunneling transistors (TFETs). That focus continued at the recent CS International Conference. In particular, Nadine Collaert discussed IMEC’s work on InGaAs homo-junction devices. Many compound semiconductor devices depend on heterojunctio... » read more

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