tag: low-power design

Mixed-Signal/Low-Power Design
By Jeff Dorsch - 14 Jul, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below
By Cadence - 13 Jul, 2016 - Comments: 0

At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 29 Jun, 2016 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to discuss new ways to increase energy efficiency in SoCs. What follows are excerpts of that conversation. SE: Looking out at the semiconductor industry there are a lot of changes underway right now. What are the biggest impacts from your perspective? Pierce: The amount of data that is being captured or sen... » read more

Performance First
By Ed Sperling - 16 Jun, 2016 - Comments: 0

Crank up the clock speed. It takes a lot more performance to run virtual reality smoothly, or to process data in the cloud, or to stream a high-definition video from a drone. And none of that compares to the amount of performance required to kill an array of disturbingly realistic zombies on a mobile device in conjunction with other players scattered around the globe. After several years of ... » read more

Big Data Meets Chip Design
By Ann Mutschler - 16 Jun, 2016 - Comments: 0

The amount of data being handled in chip design is growing significantly at each new node, prompting chipmakers to begin using some of the same concepts, technologies and algorithms used in data centers at companies such as Google, Facebook and GE. While the total data sizes in chip design are still relatively small compared with cloud operations—terabytes per year versus petabytes and exa... » read more

Tech Talk: Power Reduction
By Ed Sperling - 01 Jun, 2016 - Comments: 0

Sonics CTO Drew Wingard talks about energy processing units, and how to utilize idling circuitry to save as much as 95% of the energy spent on specific processes. [youtube vid=IZy38BfHP60] » read more

The Evolving Thermal Landscape
By Ann Mutschler - 16 May, 2016 - Comments: 0

Managing heat in chips is becoming a precision balancing act at advanced nodes and with advanced packaging. While it's important to ensure that temperatures don't rise high enough to cause reliability problems, adding too much circuitry to control heat can reduce performance and lower energy efficiency. The most common approach to dealing with these issues is thermal simulation, which requir... » read more

Power-Centric Chip Architectures
By Ed Sperling - 12 May, 2016 - Comments: 0

As traditional scaling runs out of steam, new chip architectures are emerging with power as the starting point. While this trend has been unfolding for some time, it is getting an extra boost and sense of urgency as design teams weigh a growing number of design challenges and options across a variety of new markets. Among the options are [getkc id="196" kc_name="multi-patterning"] and [getkc... » read more

Have Margins Outlived Their Usefulness?
By Aveek Sarkar - 20 Apr, 2016 - Comments: 0

To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

2.5D Becomes A Reality
By Ed Sperling - 14 Apr, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

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