tag: low-power design

The Evolving Thermal Landscape
By Ann Mutschler - 16 May, 2016 - Comments: 0

Managing heat in chips is becoming a precision balancing act at advanced nodes and with advanced packaging. While it's important to ensure that temperatures don't rise high enough to cause reliability problems, adding too much circuitry to control heat can reduce performance and lower energy efficiency. The most common approach to dealing with these issues is thermal simulation, which requir... » read more

Power-Centric Chip Architectures
By Ed Sperling - 12 May, 2016 - Comments: 0

As traditional scaling runs out of steam, new chip architectures are emerging with power as the starting point. While this trend has been unfolding for some time, it is getting an extra boost and sense of urgency as design teams weigh a growing number of design challenges and options across a variety of new markets. Among the options are [getkc id="196" kc_name="multi-patterning"] and [getkc... » read more

Have Margins Outlived Their Usefulness?
By Aveek Sarkar - 20 Apr, 2016 - Comments: 0

To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

2.5D Becomes A Reality
By Ed Sperling - 14 Apr, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Analyzing The Integrity Of Power
By Ann Mutschler - 14 Apr, 2016 - Comments: 0

Power analysis is shifting much earlier in the chip design process, with power emerging as the top design constraint at advanced process nodes. As engineering teams pack more functionality and content into bigger and more complex chips, they are having to deal with more complex interactions that affect everything from power to its impact on signal integrity and long-term reliability. That, i... » read more

Bridging The IP Divide
By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

How Many Cores? (Part 1)
By Ed Sperling - 10 Mar, 2016 - Comments: 2

The optimal number of processor cores in chip designs is becoming less obvious, in part due to new design and architectural options that make it harder to draw clear comparisons, and in part because just throwing more cores at a problem does not guarantee better performance. This is hardly a new problem, but it does have a sizable list of new permutations and variables—right-sized heteroge... » read more

Micro-Architectural Exploration for Low Power Design
By Abhishek Ranjan - 14 Jan, 2016 - Comments: 0

In the first part of this series, we had discussed the need to perform power optimizations and exploration at higher levels of abstractions where the potential to reduce the power consumption is highest. We presented the need for making coarser changes at higher level of abstractions to exploit full power saving potential. In the second part, we discussed some very potent micro-architectural te... » read more

Transistor-Level Verification Returns
By Brian Bailey - 13 Jan, 2016 - Comments: 1

A few decades ago, all designers did transistor-level verification, but they were quite happy to say goodbye to it when standard cells provided isolation at the gate-level and libraries provided all of the detailed information required, such as timing. A few dedicated people continued to use the technology to provide those models and libraries and the most aggressive designs that wanted to stri... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy