Challenges At 32nm And Beyond


Wally Rhines, chairman and CEO of Mentor Graphics, talks about what's changing in design, the effect of low power, and who's going to be doing the most advanced designs. [youtube vid=_hDk9bx4gXo] » read more

Understanding Power-Aware Verification


By Bhanu Kapoor We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for the bulk of semiconductor designs now, and it's a key re... » read more

SOI Goes Mainstream


By Ed Sperling The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips. For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, ... » read more

New Challenges For Hardware Engineers


  It used to be fun to be a chip architect. You could wake up in the morning, grab a cup of strong black coffee and run through a few power and performance tradeoff calculations before deciding on the high-level architecture. That would set the engineering direction for months, if not years. On a good day, after introducing a steady infusion of caffeine into your bloodstream, you felt like ... » read more

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