tag: lowRISC

Chip Industry Week In Review
By The SE Staff - 21 Jun, 2024 - Comments: 0

BAE Systems and GlobalFoundries are teaming up to strengthen the supply of chips for national security programs, aligning technology roadmaps and collaborating on innovation and manufacturing. Focus areas include advanced packaging, GaN-on-silicon chips, silicon photonics, and advanced technology process development. Onsemi plans to build a $2 billion silicon carbide production plant in the ... » read more

Chip Industry Technical Paper Roundup: Mar. 11
By Liz Allan - 11 Mar, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=205 /] More ReadingTechnical Paper Library home » read more

K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections
By Technical Paper Link - 07 Mar, 2024 - Comments: 0

A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

Chip Industry Week In Review
By The SE Staff - 16 Feb, 2024 - Comments: 0

By Susan Rambo, Karen Heyman, and Liz Allan. Renesas plans to acquire Altium, maker of PCB design software, for $5.9 billion. In a conference call, Renesas CEO Hidetoshi Shibata cited Altium's PCB design software and digital twin virtual modeling as key components of its future strategy. "I believe it will generate transformational value for our combined customers and our stakeholders," Shib... » read more

Chip Industry’s Technical Paper Roundup: October 24
By Liz Allan - 24 Oct, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=157 /] More Reading Technical Paper Library home » read more

LLMs For Hardware Design Verification
By Technical Paper Link - 16 Oct, 2023 - Comments: 0

A technical paper titled “LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation” was published by researchers at University of Cambridge, lowRISC, and Imperial College London. Abstract: "Test stimuli generation has been a crucial but labor-intensive task in hardware design verification. In this paper, we revolutionize this process by harnessing the power of large langua... » read more

Week In Review: Design, Low Power
By Jesse Allen - 03 Jun, 2022 - Comments: 0

Tools, IP, chips Synopsys unveiled a new data-visibility and machine intelligence-guided design optimization solution. DesignDash is complementary to the company's DSO.ai AI-driven design-space-optimization tool and provides a real-time, unified, 360-degree view of all design activities. It uses deep analytics and machine learning to extract and reveal actionable understanding from large amoun... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 03 Jun, 2022 - Comments: 0

Automotive, mobility Cruise, General Motors’ self-driving car company, obtained a permit to charge for rides in San Francisco, according to a story in Reuters. The California Public Utilities Commission, the regulatory board that can approve permits, voted 4-0 to issue “the first Phase I Driverless Autonomous Vehicle (AV) Passenger Service Deployment permit in California to Cruise LLC to a... » read more

Why RISC-V Is Succeeding
By Brian Bailey - 24 Feb, 2022 - Comments: 5

There is no disputing the excitement surround the introduction of the RISC-V processor architecture. Yet while many have called it a harbinger of a much broader open-source hardware movement, the reasons behind its success are not obvious, and the implications for an expansion of more open-source cores is far from certain. “The adoption of RISC-V as the preferred architecture for many sili... » read more

Components For Open-Source Verification
By Brian Bailey - 02 Sep, 2020 - Comments: 2

Defining an open-source verification methodology is a lot more difficult than just developing an open-source simulator. This is the reality facing open-source hardware such as RISC-V. Some people may be asking for the corresponding open-source verification, but that is a much tougher problem — and it is not going to be solved in the short term. Part one examined the reasons why open-source... » read more

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