New Design Approaches At 7/5nm

By Ed Sperling - 04 Mar, 2019 - Comments: 0

The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Tightening Margins On Heat

By Ed Sperling - 17 Jan, 2019 - Comments: 0

Stephen Crosher, CEO of Moortec, talks with Semiconductor Engineering about the impact of more accurate measurements on power, performance and reliability of designs from 40nm all the way down to 3nm. https://youtu.be/VnX-TiaMVmI » read more

Inferencing In Hardware

By Ed Sperling - 06 Dec, 2018 - Comments: 0

Cheng Wang, senior vice president of engineering at Flex Logix, examines shifting neural network models, how many multiply-accumulates are needed for different applications, and why programmable neural inferencing will be required for years to come. https://youtu.be/jb7qYU2nhoo See other tech talk videos here. » read more

5nm Design Progress

By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

In-Design Power Rail Analysis

By Ed Sperling - 17 Jul, 2018 - Comments: 0

Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

7nm Design Challenges

By Ed Sperling - 09 Jul, 2018 - Comments: 0

Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm. https://youtu.be/ZqCAbH678GE » read more

Near-Threshold Issues Deepen

By Ann Mutschler - 14 Jun, 2018 - Comments: 0

Complex issues stemming from near-threshold computing, where the operating voltage and threshold voltage are very close together, are becoming more common at each new node. In fact, there are reports that the top five mobile chip companies, all with chips at 10/7nm, have had performance failures traced back to process variation and timing issues. Once a rather esoteric design technique, near... » read more

Tech Talk: 7/5/3nm Signoff

By Ed Sperling - 12 Apr, 2018 - Comments: 0

Anand Raman, director of technical marketing at Helic, explains what's needed to improve confidence in designs at the most advanced process nodes. https://youtu.be/2O2pbMJSta4 » read more

Why Inductance Is Good for Area, Power and Performance

By Magdy Abadir - 12 Mar, 2018 - Comments: 0

By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Tech Talk: On-Chip Variation

By Ed Sperling - 01 Mar, 2018 - Comments: 0

Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more

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