tag: margin

Power Grid Analysis
By Marko Chew - 13 Jun, 2013 - Comments: 1

By Marko Chew Introduction Power grids (PGs) have consumed an increasingly larger percentage of routing resources in recent process node generations, due to lower maximum current limits imposed by the foundry. It is not uncommon to see upwards of 30% of the routing resources consumed by the PG, with correspondingly negative implications for a design’s routability. Of course, the design’... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

Margin Of Error
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better choice. But at advanced process nodes, margin also can slow performance, increase power consumption, and make it harder to achieve timing closure. The obvious solution is to reduce margin thro... » read more

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