Power Grid Analysis

A deep dive into what a PG analysis tool is and how to use it to reduce margin.

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By Marko Chew

Introduction
Power grids (PGs) have consumed an increasingly larger percentage of routing resources in recent process node generations, due to lower maximum current limits imposed by the foundry. It is not uncommon to see upwards of 30% of the routing resources consumed by the PG, with correspondingly negative implications for a design’s routability. Of course, the design’s chip area can always can be increased to reduce the routing congestion, but this increases the overall product cost. As result, the days of assuming that there is extra design margin in the PG have long passed. PG analysis has now has become a mandatory check during the physical design process.

PG analysis and verification is a fairly complex operation, with many steps in the process. While tools that support some elements of PG analysis (such as PG simulation) have been around since the early days of automated physical design tools, the verification demands of today’s designs, coupled with changes in computing architectures, have led to the development of more powerful PG analysis tools, with enhanced capabilities and greater ease-of-use. In this article, I’ll provide a whirlwind tour of the major steps in a PG analysis (without delving into too much detail, hopefully). My goal is to give you an appreciation of the complexity of PG analysis, with a glimpse into how newer PG analysis tools can help you implement this new verification requirement.

What is PG Analysis?
The negative consequences of an inadequate PG run the gamut from performance degradation to functional failures. These negative outcomes arise when one or more of a design’s PGs are not able to satisfy the following conditions:

  1. The internal voltage values are within the design tolerances
  2. The current densities are within the foundry limits

At the conceptual level, the role of power grid (PG) analysis is simply to verify these two conditions.

Internal voltage checks are needed because a typical physical design flow assumes that the PG will deliver voltage values within a limited deviation range (such as ± 10%) from the nominal values. This is the V in the process/voltage/temperature (PVT) corner case conditions used by various design creation and analysis tools, such as physical synthesis, static timing analysis, and circuit simulation.

At the same time, due to reliability considerations, there are foundry restrictions on the maximum current densities an underlying PG layout shape is allowed to have.

PG Analysis Flow
A PG analysis tool views a design as consisting of two distinct, but related, netlists (Figure 1). The design netlist contains a description of the circuit elements and the interconnections among them. The PG netlist consists of the power and ground networks associated with different voltage domains respectively. In a digital flow, the circuit elements are typically standard cells, or other hard intellectual property (IP) macros, such as register files or memory blocks.

Fig1_PG_and_Design_Networks_v02
Figure 1. PG and design networks.
Digital physical synthesis and implementation tools abstract the PG networks as a system that delivers voltage values with a limited deviation range. In contrast, PG analysis tools view the PG network as an electrical circuit consisting of resistors, capacitors, and inductors, and the design netlist as the source of the excitation to drive the analysis. The IP elements are usually modeled as current sources and sinks that pull or push currents from the PG networks (Figure 1 Figure 2).).

Fig2_PG_Circuit_Network_v02Figure 2. Parasitic PG circuit network.

The order of operations in a PG analysis flow is shown in Figure Figure 3. The first step, typically referred to as PG extraction, is to generate the equivalent circuit representation of the PG network, consisting of parasitic resistance and capacitance components, as well as intentional capacitance elements such as decoupling capacitors. Concurrent with the PG extraction is the pre-computation, or modeling, of the IP blocks’ interaction with the PG network through pre-defined connection or port points under various conditions (such as input slew and output loading capacitance). This information is usually stored in a power library, which contains the PG interaction models of two or more IP blocks.

Fig3_Generic_PG_Flow

Figure 3. Generic P/G analysis flow.
Next is the generation of the realistic worst-case profile, which is an estimation of the various IP blocks’ PG activity based on realistic circuit behavior, such as the percentage of design switching within a clock cycle (since not all gates will be active).

The power grid simulator then accepts the equivalent PG circuit, and uses the current information contained in the power library to drive the simulation process. During the simulation phase, excitation vectors are applied to the PG network, and the voltages and currents throughout the PG network are computed.

At the completion of the simulation phase, the voltage values at the PG pins of each IP block and the current values of the parasitic PG elements are submitted for analysis. The analysis phase crawls through these simulation results to check for deviations from the design requirements and foundry limits.

If PG issues are identified, the last step is to define and limit the set of possible root causes. Once a limited set of possible root causes is identified, the repair phase can be initiated.

PG Flow Components
Now let’s take a closer look at some of the specifics of the PG flow:

IP Block Modeling
Most PG analysis tools typically abstract block interactions with the PG, rather than expose the underlying transistors during the PG simulation. Abstraction is performed because PG analysis does not require the same accuracy as transistor-level circuit simulation, and abstraction provides a significant speed advantage.

With the power model abstraction, the IP block interacts with the PG only at well-defined pin locations (Figure 4). For simple IP blocks, such as standard cells, a single pin is sufficient for each PG net. For more complex IP blocks, such as embedded memories, there can be multiple pins associated with each PG net.

Fig4_IP_Block_Power_Modeling
Figure 4. IP block power models.
Each PG pin is modeled as a current source and capacitor (Figure 5). An IP block’s current source and capacitor values are typically computed by running circuit simulations of the underlying transistor netlist annotated with the layout parasitic information (LPE). The results of the circuit simulation under different neighboring contexts (such as input slew and output loading capacitance) is then tabulated and stored in a power library.

Fig5_PG_Pin_ModelFigure 5. PG pin model.

PG Extraction
The PG extraction step is one of the most computationally demanding steps in the flow, due to the number of objects in a PG layout. Figure 6 compares the number of shapes for PG nets in various power domains to those from the top 20 signal nets. PG net layout object counts can easily span an 8-decade range (10E8) from nets with the largest to smallest shape counts, and these counts are prior to resistance fracturing, which can easily increase the counts by a factor of 10-100x. The internal structure of a signal net extractor is not typically designed for these very large shape counts.

Fig6_Shape_Count_Compare
Figure 6. Shape counts comparison between signal nets and PG nets.
However, typical signal nets never have large shape counts, because physical implementation tools insert buffers to control the interconnect parasitics that a given driver will see, to reduce the chance of large interconnect delays.

With this large number of shape counts, an out-of-the-box signal net extraction engine will have both runtime and memory issues when handling a typical PG network. In addition, PGs have certain characteristics, such as regularity and less-constrained accuracy requirements, that a specialized PG extraction tool can take advantage of for memory and runtime tradeoffs.

PG Simulator
A power grid simulator solves the current nodal equations as specified by Kirchoff’s current law (KCL), which specifies that the sum of the currents entering and leaving a given node should be zero. First, the simulator formulates the equations, based on the parasitic PG network, PG pad/bump voltage sources, and IP block current sources (Figure 7).

Fig7_Equation_Formulation
Figure 7. Equation formulation.
After appropriate transformations to allow more efficient computation, the PG simulator solves the system of equations (Figure 8). The solution is a set of node voltages, which are represented by the vector .

Fig8_Matrix Form
Figure 8. Matrix form and solution.
Energy storage elements such as capacitors and inductors are handled similarly by appropriate discretization of their time dependencies (Figure 9) for the integration computations.

Fig9_Energy_Storage
Figure 9. Energy storage elements.

Legacy PG simulators were developed during the era when multi-core and distributed computing systems were rare, due to their high cost. Over the past few years, there have been algorithmic advancements made in computing A^(-1), which is the core calculation of a PG simulator. These advances take advantage of multi-core shared memory configurations and relatively low-cost distributed computing (non-shared memory) infrastructures. A PG simulator that incorporates these new solver algorithms has the potential of faster runtimes and the ability to handle larger PG design sizes compared to legacy PG simulator algorithms.

Realistic Worst Case Profile Generator
One of the critical steps in PG analysis is the creation of the excitation vectors. The excitation vector should represent as closely as possible the true activity of the IP blocks, as represented by active current sources and their values. For example, in a typical design, it is unlikely that all the IP blocks will be switching simultaneously, so an excitation vector with 100% of the current sources active is not realistic, and would generate inaccurate results.

The two types of PG analysis, static and dynamic, differ in the nature of current source/sink values. In static analysis, the current sources are constant values representing the leakage currents and average currents drawn in normal circuit operations (Figure 10). The value of is obtained by best guess using engineering insight. Since there is no time dependency, the static analysis only needs to compute the DC solution of the purely resistive PG network driven by constant current source values.

Fig10_Static_Current_Value
Figure 10. Static current value.

In dynamic analysis, the current sources can vary as function of time, and represent waveforms of the current drawn from and pushed into the PG grids.

In static analysis, the profile generator emits a set of k_fudge values. In dynamic analysis, the profile generator emits a partial ordering of current source values representing activity of the IP blocks as function ofas time. In either case, the most accurate data to drive the profile generator is the highest activity trace from gate level simulations.

Unfortunately, these simulation results are often not available for a variety of reasons, ranging from too voluminous a simulation data set to pending (still running) simulations. Consequently, legacy approaches resorted to the use of heuristics, which resulted in a lack of correlation to a design’s actual PG behavior, as well as being difficult to implement without expert knowledge.

To improve the correlation, it is important to incorporate as much available information as possible during the profile generation step. One valuable information source is the activity profiles from earlier implementations of blocks. Another is the power estimate generated during the synthesis phase. Having the profile generator automatically incorporate these information sources has the potential to allow even novice users to produce highly-correlated PG analysis results.

Analysis
Once the current and voltage values have been computed for the PG network, two categories of checks must be run to satisfy those two conditions I discussed at the beginning of the article. The first category is driven by the reliability of the interconnection layers, while the second category is related to the voltage values seen at the IP’s cell PG pins.

Interconnection layer reliability is determined by electromigration (EM) phenomena, where ionized atoms within a conductor with an applied electric field will actually move from their original position, with negative consequences. The standard EM reliability equation variants are derived from Black’s equation, which relates failure rates to several parameters, of which current and temperature are the most important (Figure 11). These variants usually have layout shape dependencies, such as adjustments for a layout shape’s width and length.

Fig11_Blacks_Equation
Figure 11. Black’s original failure equation.

The IR drop analysis is much simpler, and involves checking for actual voltage node values against tolerances. For example, typical static analysis limits would be 1% from the nominal values, such as 10mV for a 1.0 v nominal voltage. Dynamic analysis limits would be higher, such as 5%, or 50 mV for 1.0v nominal.

Root Cause Diagnosis
Narrowing the possible causes of a PG issue is a difficult task, due to myriad possibilities, and usually requires detailed knowledge of the design. For designers who are not specialists in PG analysis, it is important for a PG analysis tool to not only encode the best practices of a PG diagnostic expert, but also to display the information and cues in an easily accessible graphic user interface (GUI). A GUI that can cross-probe and annotate the native layout visualization interface of the physical implementation tool used to generate the design can help even novice users localize potential causes of the PG analysis issues.

Summary
The two important roles of power grid analysis are 1) to verify that PG voltage values are within the design assumptions, and 2) to verify that PG currents do not exceed the foundry current limitations. Ensuring that these two conditions are met requires both a complex computational intensive flow and expert knowledge of PG networks and their components. New PG analysis tools are emerging that have algorithm improvements to improve runtimes and reduce memory footprint, and which can automate the PG analysis process and encapsulate much of that expert knowledge, enabling all designers to perform PG analysis and debug PG issues. Using these new tools can speed up time to market, while ensuring today’s low power designs will meet performance and reliability targets.

—Marko Chew is a Technical technical Marketing marketing Engineer engineer in the Design-to-Silicon Division of Mentor Graphics.