Design Flows At 5nm And Beyond

It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40 nanometers was the most advanced node that I ever designed SoCs at and, although it wasn’t easy back then, it pales against the myriad of challenges facing designers today. Back then, compartmentalization of function and roles was relatively easy. We do ... » read more

Margin Call

Ever since Moore’s Law passed 65nm, the discussion has focused on power versus performance. Do you run a chip faster and hotter, or do you keep performance about the same from one chip to the next and improve battery life. At 28nm and beyond, there are other factors that begin to weigh into this discussion. One is reliability. Can a chip developed at the forefront of Moore’s Law be as re... » read more

Less Room For Error

By Ed Sperling Say goodbye to fat design margins in advanced SoCs. The commonly used method of adding extra performance or area into semiconductors to overcome variability in manufacturing processes or timing closure issues has begun to create problems of its own. While there was plenty of slack available at 90nm, adding margins at 45nm and 32nm disrupts performance or eats into an increasing... » read more