tag: memory controller

HBM3E Memory: Break Through to Greater Bandwidth
By Rambus - 03 Apr, 2024 - Comments: 0

Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI training. HBM3 is the third major generation of the HBM standard, with HBM3E offering an extended data rate and the same feature set. The Rambus HBM3E/3 Controller provides industry-leading performance to 9.6 Gb/s, enabling a memory throughput of over 1.23 TB/s for training reco... » read more

HBM3 Memory: Break Through to Greater Bandwidth
By Rambus - 13 Dec, 2023 - Comments: 0

Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI/ML and other high-performance computing workloads. HBM3 as the latest generation of the standard raises data rates to 6.4 Gb/s and promises to scale even higher. The Rambus HBM3 controller provides industry-leading support of the extended roadmap for HBM3 with performance to 9.6... » read more

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)
By Technical Paper Link - 13 Sep, 2023 - Comments: 0

A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. Abstract: "We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the perfo... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangement
By Arm - 12 Oct, 2022 - Comments: 0

Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with m... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

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