tag: memory design

Rethinking Memory
By Karen Heyman - 22 Jan, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the path forward for memory in increasingly heterogeneous systems, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; and Frank Schirrmeister, vice... » read more

The Future Of Memory
By Karen Heyman - 11 Jan, 2024 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of off-chip memory on power and heat, and what can be done to optimize performance, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; a... » read more

MRAM Getting More Attention At Smallest Nodes
By Karen Heyman - 10 Aug, 2023 - Comments: 2

Magneto-resistive RAM (MRAM) appears to be gaining traction at the most advanced nodes, in part because of recent improvements in the memory itself and in part because new markets require solutions for which MRAM may be uniquely qualified. There are still plenty of skeptics when it comes to MRAM, and lots of potential competitors. That has limited MRAM to a niche role over the past couple de... » read more

Meeting The Major Challenges Of Modern Memory Design
By Synopsys - 26 Apr, 2023 - Comments: 0

Memory lies at the heart of every electronics application, and demand is growing all the time. Users want ever greater capacity, throughput, and reliability. At the same time, time to market (TTM) goals and competitive pressures mandate that memories be developed in ever shorter project schedules. These requirements put enormous pressure on designers of discrete memory chips, memory dies in 2.5... » read more

Digitizing Memory Design And Verification To Accelerate Development Turnaround Time
By Anand Thiruvengadam - 10 Oct, 2022 - Comments: 0

By Anand Thiruvengadam, Farzin Rasteh, Preeti Jain, and Jim Schultz Some digital design and verification engineers imagine that their colleagues working on analog/mixed-signal (AMS) chips are jealous. After all, the digital development flow has enjoyed the benefits of increased automation and higher levels of abstraction for many years. Hand-instantiated devices and manual interconnection we... » read more

Comprehensive Model of Electron Conduction in Oxide-Based Memristive Devices
By Technical Paper Link - 03 Feb, 2022 - Comments: 0

Abstract "Memristive devices are two-terminal devices that can change their resistance state upon application of appropriate voltage stimuli. The resistance can be tuned over a wide resistance range enabling applications such as multibit data storage or analog computing-in-memory concepts. One of the most promising classes of memristive devices is based on the valence change mechanism in oxide... » read more

Time To Rethink Memory Chip Design And Verification
By Anand Thiruvengadam - 12 Aug, 2021 - Comments: 1

It’s no secret to anyone that semiconductor development grows more challenging all the time. Each new process technology node packs more transistors into each die, creating more electrical issues and making heat dissipation harder. Floorplanning, logic synthesis, place and route, timing analysis, electrical analysis, and functional verification stretch electronic design automation (EDA) tools... » read more

System Bits: Oct. 6
By Ann Mutschler - 06 Oct, 2015 - Comments: 0

Tiny graphene pores for sensors In fundamental work that will likely guide current and future graphene membrane design principles in years to come, MIT researchers have created tiny pores in single sheets of graphene that have an array of preferences and characteristics similar to those of ion channels in living cells, and which could be useful as sensors. The researchers pointed out that e... » read more

Higher Frequencies Mean More Memory
By Ann Mutschler - 16 Jan, 2015 - Comments: 0

As SoCs get more complex, whether due to higher frequencies or adding more functionality, there is a spillover effect on bandwidth, [getkc id="22" kc_name="memory"] and power. There is no simple way to just turn up the clock frequency in a complex [getkc id="81" kc_name="SoC"]. That relatively straightforward objective will likely require more power domains, more cores, more ways to move sig... » read more

The Rise Of Layout-Dependent Effects
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

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