What’s Changing In DRAM

By Ed Sperling - 22 Jan, 2024 - Comments: 0

More data requires more processing and more storage, because that data needs to be stored somewhere. What’s changing is that it’s no longer just about SRAM and DRAM. Today, multiple types of DRAM are used in the same devices, each with its own set of tradeoffs. C.S. Lin, marketing executive at Winbond, talks about the potential problems that causes, including mismatches in latency, and high... » read more

CiM Integration For ML Inference Acceleration

By Technical Paper Link - 16 Jan, 2024 - Comments: 0

A technical paper titled “WWW: What, When, Where to Compute-in-Memory” was published by researchers at Purdue University. Abstract: "Compute-in-memory (CiM) has emerged as a compelling solution to alleviate high data movement costs in von Neumann machines. CiM can perform massively parallel general matrix multiplication (GEMM) operations in memory, the dominant computation in Machine Lear... » read more

SRAM’s Role In Emerging Memories

By Karen Heyman - 05 Jan, 2024 - Comments: 1

Experts at the Table — Part 3: Semiconductor Engineering sat down to talk about AI, the latest issues in SRAM, and the potential impact of new types of memory, with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part one of this conversation can be ... » read more

The Uncertain Future Of In-Memory Compute

By Karen Heyman - 13 Dec, 2023 - Comments: 0

Experts at the Table — Part 2: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, chief technology officer at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part one of this conversation can be found here and part 3 is h... » read more

SRAM In AI: The Future Of Memory

By Karen Heyman - 09 Nov, 2023 - Comments: 0

Experts at the Table — Part 1: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part two of this conversation can be found here and part three is here. [L-R]: ... » read more

Power/Performance Bits: May 6

By Jesse Allen - 06 May, 2019 - Comments: 0

Compressing objects Computer scientists at MIT propose a way to improve data compression in memory by focusing on objects rather than cache lines. "The motivation was trying to come up with a new memory hierarchy that could do object-based compression, instead of cache-line compression, because that's how most modern programming languages manage data," said Po-An Tsai, a graduate student at... » read more

Tech Talk: Data-Driven Design

By Ed Sperling - 14 Jun, 2018 - Comments: 0

Steven Woo, distinguished inventor at Rambus, talks about memory hierarchies and how they are changing as the amount of data continues to grow. https://youtu.be/4FwZ1YeQa18 » read more

New Memory Approaches And Issues

By Ed Sperling - 14 Mar, 2016 - Comments: 1

New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

Architecturally Optimizing Memory Bandwidth

By Ann Mutschler - 27 Mar, 2015 - Comments: 0

Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?