Alleviating the DRAM Capacity Bottleneck in Consumer Devices with NVMs


A new technical paper titled "Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD" was published by researchers at ETH Zurich, University of Illinois Urbana-Champaign, Google, and Rivos. Abstract Excerpt "DRAM scalability is becoming a limiting factor to the available memory capacity in... » read more

State of the Art And Future Directions of Rowhammer (ETH Zurich)


A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon in... » read more

Learn The Architecture — Memory System Resource Partitioning And Monitoring (MPAM) Overview


This guide introduces the Memory System Resource Partitioning and Monitoring (MPAM), an optional addition to the Arm architecture to support memory system partitioning. MPAM is documented in the Memory System Resource Partitioning and Monitoring (MPAM), for A-profile architecture Arm Architecture Reference Manual Supplement. Click here to read more. » read more

ETH Zurich: PIM (Processing In Memory) Architecture, UPMEM & PrIM Benchmarks


New paper technical titled "Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture" led by researchers at ETH Zurich. Researchers provide a comprehensive analysis of the first publicly-available real-world PIM architecture, UPMEM, and introduce PrIM (Processing-In-Memory benchmarks), a benchmark suite of 16 workloads from different application domai... » read more

Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware


Abstract "Many modern workloads such as neural network inference and graph processing are fundamentally memory-bound. For such workloads, data movement between memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bo... » read more

SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems


Abstract "Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwi... » read more