tag: Mentor

Auto Sector Leads The Way In IC Security
By Ann Mutschler - 03 Apr, 2025 - Comments: 0

Concerns about chip and system security are beginning to bear fruit in some markets, driven by the overlap in safety and security in automotive applications and the growing value of algorithms and complex systems in others. But how and when that security is implemented is still all over the map, and so is its effectiveness. The reasons are as nuanced as the designs themselves, which makes it... » read more

Stakes Are High For Aerospace, Defense IC Designs
By Liz Allan - 03 Apr, 2025 - Comments: 0

Chips destined for the skies or armed forces need extra everything. They require higher layers of abstraction to simulate all the moving parts in the field, high-reliability testing for harsh environments, in addition to system-level test. They also need radiation-hardening and ceramic materials for space, extra safety layers, and advanced security techniques. As in the automotive sector, th... » read more

Chip Aging Opens Up New Attack Vectors
By Adam Kovac - 03 Apr, 2025 - Comments: 0

The longer a piece of silicon is out in the field the more prone it becomes to a cyberattack, raising questions about the optimal longevity of circuits and the impact of extending their lifetimes. This is particularly challenging for safety- and mission-critical applications, where the cost of development can run as high as $100 million for some of the most complex designs. Chipmakers want t... » read more

HyperLynx
By Siemens EDA - 03 Apr, 2025 - Comments: 0

You gain the full power of HyperLynx when it is fully integrated as part of the Xpedition PCB design flow. Yet, it also interfaces with most PCB layout tools, allowing any engineer to quickly import and set up their PCB designs for analysis, regardless of their existing toolset. And because its progressive verification methodology analyzes a design in stages, HyperLynx locates issues earlier an... » read more

Blog Review: Apr. 2
By Jesse Allen - 02 Apr, 2025 - Comments: 0

Synopsys’ Meenakshy Ramachandran explores how DisplayPort Automotive Extensions help meet functional safety and security standards for the increasingly higher-resolution and more immersive in-vehicle displays in connected, autonomous, shared, and electric vehicles. Siemens’ Gabriella Leone and Michael Munsey discuss the need for a collaborative semiconductor business platform and how to ... » read more

Chip Industry Week In Review
By The SE Staff - 28 Mar, 2025 - Comments: 0

McKinsey issued a new report on the state of the chemical supply chain for semiconductors in the U.S., citing potential shortages of high-purity materials such as tungsten, aluminum and copper, lack of access to CMP slurries and photoresists for EUV, and rising competition for high-k precursors that can fetch higher prices outside of the U.S. CSIS weighed in on the U.S. goverment's recent ... » read more

How AI And Connected Workflows Will Close The Verification Bottleneck
By Harry Foster - 27 Mar, 2025 - Comments: 0

For decades, verification has been the unsung hero of chip development—quietly catching bugs before they reach silicon. But as semiconductor complexity has skyrocketed, verification has turned into the bottleneck of development cycles. This challenge has a name: Verification Productivity Gap 2.0. Back in the early 2000s, the Verification Productivity Gap 1.0 emerged when design complexi... » read more

Challenges In Managing Chiplet Resources
By Ann Mutschler - 27 Mar, 2025 - Comments: 0

Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

First-Time Silicon Success Plummets
By Ed Sperling - 27 Mar, 2025 - Comments: 0

First-time silicon success is falling sharply due to rising complexity, the need for more iterations as chipmakers shift from monolithic chips to multi-die assemblies, and an increasing amount of customization that makes design and verification more time-consuming. Details from a new functional verification survey[1] highlight the growing difficulty of developing advanced chips that are both... » read more

A Novel Approach For HW/SW Co-Verification
By Siemens EDA - 27 Mar, 2025 - Comments: 0

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verificati... » read more

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