tag: Mentor Graphics

Raising The Stakes For IP
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market. The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occu... » read more

Too Hot To Handle
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler It used to be that a device could be designed to a thermal design power. The worst case power scenario would be imagined, and the device would be designed with that in mind. But those good old days are gone. Especially for consumer devices, how a device is going to behave with respect to time, or how people are going to use it, must be understood as completely a... » read more

Managing Electrical Communications Better
By Ann Mutschler - 14 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the electrical components of signal paths between IC, package, board and system is no small task, and it’s only growing in complexity. Understanding how to correctly optimize the communications within a system is critical given that the I/O power is becoming a significant portion of the overall chip power as the number of bits and the speed at which t... » read more

New Issues In Signoff
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 09 Feb, 2013 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

Experts At The Table: Latency
By Ed Sperling - 01 Feb, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance engineering sat down to discuss latency with Chris Rowen, CTO at Tensilica; Andrew Caples, senior product manager for Nucleus in Mentor Graphics’ Embedded Software Division; Drew Wingard, CTO at Sonics; Larry Hudepohl, vice president of hardware engineering at MIPS; and Barry Pangrle, senior power methodology engineer at Nvidia. What follows are exce... » read more

SoC Architects Face Big Challenges
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Inside The System-Level Supply Chain
By Ed Sperling - 31 Jan, 2013 - Comments: 0

System-Level Design sat down to discuss supply chain issues with Bill Chown product marketing director for the system-level engineering division at Mentor Graphics and a longtime participant in a number of standards efforts across the semiconductor design industry. What follows are excerpts of that conversation. SLD: What’s happening with system engineering as chip design/manufacturing mo... » read more

Experts Panel And Tutorial At DVCon
By Graham Bell - 31 Jan, 2013 - Comments: 0

Besides our usual exhibit at the Design and Verification Conference in Santa Clara at the end of next month, Real Intent has organized a panel and a half-day tutorial that highlights some of the changes happening in our industry—and which may have been overlooked. The panel addresses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design a... » read more

Keep The Silos
By Jon McDonald - 31 Jan, 2013 - Comments: 0

By Jon McDonald I’ve had a couple of conversations recently in which software developers expressed that they have little interest in working with hardware or systems developers. The general sentiment seemed to be “when [a place commonly regarded as extremely hot] freezes over” they might consider it. Perhaps for those living in northern climates there may be a possibility of this freeze,... » read more

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