tag: Mentor Graphics

Experts At The Table: Stacked Die Reality Check
By Ed Sperling - 27 Aug, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of market... » read more

Inflection Points Ahead
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Engineering challenges have existed at every process node in semiconductor designs, but at 20nm and beyond, engineers and executives on all sides of the industry are talking about inflection points. An inflection point is literally the place where a curve on a graph turns down or up, but in the semiconductor industry it’s usually associated with the point at which a progres... » read more

Dealing With Test More Effectively
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ed Sperling Shrinking geometries are starting to have the same effect on test as they are on other parts of an SoC, with the focus shifting from area to leakage, heat, noise, signal integrity, and the impact on overall system performance. The warning that design teams have to consider test much earlier in the design was issued to chipmakers years ago and largely ignored. At 28nm that war... » read more

Experts at the Table: Stacking the Deck
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D-IC adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of EDA2ASIC Consulting... » read more

Best Practices In Verification
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry about simulator performance (i.e., how fast the simulator runs a particular test case), but the introduction of constrained-random stimulus and functional coverage and associ... » read more

Being Different Is Bad
By Ed Sperling - 23 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Today’s SoCs contain as much as 80% existing IP that either has been re-used from previous projects or obtained from a third party. Models are created of this hardware IP, as well as new portions of the design, in order to create a virtual prototype that allows the engineering team to see the complete system by running software and applications. While this a... » read more

Designing In The Rain
By Jon McDonald - 23 Aug, 2012 - Comments: 0

By Jon McDonald Recently I was running some errands on my motorcycle when I got caught in the rain. Living in Florida, this is a fairly common summer occurrence. Generally, as long as it’s not too much of a deluge, I can continue through to my destination and dry off when I arrive. I always get concerned looks from those going by in their enclosed vehicles—from some, “concerned” mig... » read more

FPGA Design And Verification in Mechatronic Applications
By Various Writers - 23 Aug, 2012 - Comments: 0

The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can requirements be expressed for a system that, while it contains digital elements, is fundamentally non-digital? Fortunately an executable HDL exists that extends the capabilities of the digital VHDL languag... » read more

Development of Complex Multicore Systems: Tracing Challenges and Concept (Part One)
By Various Writers - 23 Aug, 2012 - Comments: 0

This white paper is the first paper of a two-part Mentor Embedded multicore white paper series. In this paper, the challenges software developers face when developing, debugging, and validating software applications for a complex multicore system will be discussed. The paper also highlights some of the questions around hardware resource usage, tracing aids, tracing domains, and concepts for col... » read more

Experts At The Table: Challenges At 20nm
By Ed Sperling - 17 Aug, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

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