tag: Mentor Graphics

SoCs Go Mainstream
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling The monolithic ASIC, which has been the bread-and-butter of chipmakers for decades, is giving way to systems on a chip among mainstream chipmakers and at mainstream process nodes. This shift has been overhyped, overpromised and slow to materialize. While SoCs have been common for years in mobile electronics and for high-performance platforms such as gaming consoles, they have... » read more

Cycle-Accurate Models?
By Jon McDonald - 22 Mar, 2012 - Comments: 0

By Jon McDonald I was sitting in a meeting this week and someone made the statement, “I have to have a cycle-accurate model.” This was a meeting discussing early delivery of system models for software development, performance and power analysis. The final RTL didn't even exist for the device in question, yet somehow the thinking was that a “cycle-accurate” model was required. I hear th... » read more

New Winners And Losers
By Ed Sperling - 22 Mar, 2012 - Comments: 0

The realignment of the semiconductor industry has begun, most of it beneath the radar screen. In a disaggregated supply chain, any piece in isolation looks insignificant. But taken together, these shifts begin to paint a picture of a broad realignment and refocusing of the entire industry that ultimately will cement the fortunes of some and create new winners and losers out of others. The fi... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 09 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

The Trouble With Power Models
By Ed Sperling - 08 Mar, 2012 - Comments: 0

By Ed Sperling Talk with any large systems vendor about power modeling and, with very few exceptions, they’re still using a mix of spreadsheets and lower-level models—no matter how far along they are in ESL adoption and in modeling other parts of an IC. Power has crept up on even the biggest companies, which have never really figured out how to implement it into their design flows. For ... » read more

Flexibility Vs. Portability In Emulation
By Ann Mutschler - 08 Mar, 2012 - Comments: 0

Complete and exhaustive verification of low-power designs requires a substantial effort and part of this includes running real applications on the hardware. Simulators fall short as designers realize that the so-called testbenches they create are artificial and don’t necessarily represent typical applications. As such, this is the sweet spot for emulators, also known as hardware accelerators,... » read more

Avoiding Chip Melt
By Ed Sperling - 08 Mar, 2012 - Comments: 1

By Ann Steffora Mutschler Assertions. Just the term conjures images of writing boring lines of code to feed into a simulator. But for engineering teams working at the 40nm node, the pain of making sure their verification is complete and accurate is real—and so is the potential for literally melting silicon if something goes wrong. With this in mind, ‘boring’ goes out the window and gets ... » read more

Intel vs. AMD: Who’s Right?
By Barry Pangrle - 08 Mar, 2012 - Comments: 0

By Barry Pangrle It’s all about the system. One energy-efficient component doesn’t an energy-efficient system make. There were two big announcements recently made by the industry’s two x86 designers. One was by Intel announcing its new Sandy Bridge Xeon Processor E5-2600 product family, and the other one was by AMD announcing its planned acquisition of SeaMicro. Both of these announce... » read more

Colorblind—Colorless versus Two-Color Double Patterning Design
By David Abercrombie - 05 Mar, 2012 - Comments: 0

By David Abercrombie People are always asking “What should I expect when I start designing at 20nm using double patterning?” It’s a good question, but in many real aspects, the answer is “It depends,” and that is not very satisfying to hear. The way that a designer will interact with the constraints that double patterning (DP) brings is very dependent on the design methodology used. ... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

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