tag: Mentor Graphics

Pathfinding For Power And Heat
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling There are many ways to measure power and heat in an IC, and each one of them adds tremendous value to a design. But there are still holes, and those holes are just beginning to get filled. Power and heat have emerged as two of the most persistent problems in advanced designs, and there is no single or simple way to tackle either of them. Nevertheless, there is at least progre... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 24 Feb, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Ap... » read more

Derivative ICs: A Look At The Options
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ann Steffora Mutschler With the cost of designing and producing even moderately advanced SoCs skyrocketing, semiconductor companies and systems houses must find ways to defray the cost across a larger number of end uses than ever. As such many companies have adopted a platform-based derivative design approach, with that the platform serving as the first SoC design of a new family. That s... » read more

Different Tradeoffs
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences. What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to i... » read more

Market Catches Up With Verification IP
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling Ever since verification IP was introduced it was seen as something that should be given away with purchased IP. The result was limited investment by IP vendors, frustration on the part of IP customers, and a market opportunity that nearly fizzled before it even began. But as the amount of commercially developed IP content continues to grow in ICs, the potential interactions ... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 22 Feb, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wha... » read more

Roundtable: ESL Grows As Processes Shrink
By Ed Sperling - 22 Feb, 2012 - Comments: 0

System-Level Design talks with Steve Bailey of Mentor Graphics, Michael (Mac) McNamara of Cadence Design Systems, Ghislain Kaiser of DOCEA Power and Shawn McCloud of Calypto about what will propel growth in the system-level design tools marketplace. [youtube vid=yBhLLN40mSE] » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 17 Feb, 2012 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

Mechanical Meets Electrical
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ed Sperling For the first part of the 20th century mechanical engineering dominated almost everything in technology. For the second half, once the transistor and the integrated circuit became well entrenched, those two disciplines largely divided up the tech market. More recently, however, they are being forced to collaborate in teams that historically had nothing in common. While the co... » read more

Margin Of Error
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better choice. But at advanced process nodes, margin also can slow performance, increase power consumption, and make it harder to achieve timing closure. The obvious solution is to reduce margin thro... » read more

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