tag: Mentor Graphics

When Worlds Collide: Saving Power In Communications Applications
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler The interplay of hardware and software is a given in every device that contains a semiconductor chip, but is typically felt more acutely in communications applications given the extremely close dependencies for everything power-related. Managing power in these situations just gets more challenging as consumers demand more and better applications on their tablets, smar... » read more

The Next Big Challenge
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Software is the next big target in the quest to make electronics more energy efficient, but it’s proving a far bigger challenge than most systems architects originally believed it would be. There are several very large big problems to deal with in software. Writing efficient code for small processors isn’t one of them. In fact, the proliferation of small processors across... » read more

Status Report: Power-Aware Design Flow
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler While the term “design flow” can be a moving target, there are some specific requirements for a low-power/power-aware tool flow. Looking at this from a high level, where is the industry today, and where is it headed? There are really two sides to power, which are almost like two sides of the same coin: power consumption and power integrity. And both of those ar... » read more

Rethinking Good Enough
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Power has been elevated from an afterthought to one of the top considerations and tradeoffs in SoC design, edging out performance and area in many cases and in some cases even cost and features. Tradeoffs in design always change, depending upon what the most pressing concern is among consumers at any time. For decades, performance was always the top of anyone’s list, follow... » read more

How Long Will 28nm Last?
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler As soon as a next generation semiconductor manufacturing process node is out, bets are taken on just how long the current advanced process node will last. The 28/20nm transition is no exception. There is certainly a benefit to moving from 40nm to 28nm. The  availability of high-k/metal gate technology offers quite a few advantages in terms of power reduction... » read more

Fill Challenge Solved: Why SmartFill is as Good as it Sounds
By Jean-Marie Brunet - 12 Jan, 2012 - Comments: 0

by Jean-Marie Brunet Among the many steps involved with chip design, there is one known by the deceptively simple name of “fill.” Fill involves adding shapes or polygons to the design that are structural, not logical. That is, they ensure manufacturability by making sure each layer (metal, poly, diffusion) has a proscribed density. As easy as this sounds, fill can be tricky, and the fill... » read more

Undervolting & Underclocking
By Barry Pangrle - 12 Jan, 2012 - Comments: 0

By Barry Pangrle Last month we looked at record-breaking clock frequencies accompanied by voltage levels over 2V for some high-speed x86 processors. This month we’re going to go in the opposite direction—reducing the voltage and clock frequency to reduce power. Our processor of choice is the AMD A8-3850, a 100W, 2.9 GHz, quad-core, x86 processor that also incorporates 400 “Radeon core... » read more

Experts At The Table: Making Software More Energy-Efficient
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss software and power with Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Pete Hardee, marketing director at Cadence; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior vice president and general manager of Apache Design, and Bill Neifert, CTO of Carbon Design Systems. What follows are excerpts of that conversation. LPE: Softw... » read more

Making Software Better
By Ed Sperling - 11 Jan, 2012 - Comments: 0

Low-Power Engineering talks about what will make software more energy-efficient with Pete Hardee, marketing director at Cadence; Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior VP and General Manager of Apache Design, and Bill Neifert, CTO of Carbon Design. [youtube vid=Jxquj8K8_BA] » read more

Rebalancing Power, Performance And Area
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ed Sperling The tradeoffs between performance, power and area are being fine-tuned to a degree never seen before in the IC business, driven partly by complexity, partly by better tools, and partly by the need to gain a competitive edge in specific applications. Just being able to make these kinds of tradeoffs is a technological feat that marries everything from high-level modeling and sy... » read more

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