Blog Review: June 22


A Lam Research writer investigates the challenges that lie ahead for interconnects and whether current technologies will find new life or be replaced by new strategies. There's a greater force powering Moore's Law, says Cadence's Paul McLellan, who points to the vast amount of transistors being used for memory. Mentor's Robert Bates considers the challenges of securing in-hospital network... » read more

A Pattern Of Success: Calibre Pattern Matching


Calibre Pattern Matching allows you to define specific geometric configurations as visual patterns, directly from a design layout. With this visual representation, Calibre Pattern Matching opens up a whole new way to define design rules for both established and advanced nodes, and enables a wide range of innovative applications across design, verification, and test. This white paper introduces ... » read more

Photonics Moves Closer To Chip


Silicon photonics is resurfacing after more than a decade in the shadows, driven by demands to move larger quantities of data faster, using extremely low power and with minimal heat. Until recently, much of the attention in photonics focused on moving data between servers and storage. Now there is growing interest at the PCB level and in heterogeneous multi-chip packages. Government, academi... » read more

The Week In Review: IoT


M&A Samsung Electronics will buy Joyent, a provider of public and private cloud services. The Korean company said the purchase will give Samsung a cloud platform for the Internet of Things, mobile devices, and cloud-based software and services. “Samsung brings us the scale we need to grow our cloud and software business, an anchor tenant for our industry leading Triton container-as-a-ser... » read more

The Week In Review: Design


Tools Synopsys uncorked the latest version of its software for the design of optical communication systems and photonic integrated circuits at the signal propagation level, adding a new interface and expanding the software's application design libraries. Mentor Graphics said it would provide a variety of tools to support the new Zynq UltraScale+ MPSoC devices from Xilinx, dual-core field-... » read more

The Secret to Reaching Rapid Verification Closure


Every design team is looking to reduce RTL verification time in order to meet aggressive schedules. Successful teams have moved their level of design abstraction up to the C++ or [gettech id="31018" comment="SystemC"] level and employ [getkc id="105" comment="high-level synthesis"] (HLS) within their design flow. By taking advantage of this high-level description, these teams also plug into int... » read more

System-Level Verification Tackles New Role


Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

Blog Review: June 15


Synopsys' Marc Greenberg shares a somber and personal story on the need to get ADAS to as many drivers as possible. From the Linley IoT conference, Cadence's Paul McLellan features a talk on protecting edge nodes and the three big steps towards IoT security. Mentor's Avidan Efody presents a lighthearted reminder on the basics of ISO 26262 terminology. Just how much security is enough? ... » read more

An Introduction to Reducing Dynamic Power Using PowerPro


At many companies, the job of power reduction is left to power experts. These experts have built up knowledge and methodologies over many years, which they repeatedly apply to designs in their groups. This approach is very narrow and it not scalable across multiple groups in the company. Companies have begun to realize the limitations of this approach. More and more RTL designers are being task... » read more

Plotting The Next Semiconductor Road Map


The semiconductor industry is retrenching around new technologies and markets as Moore's Law becomes harder to sustain and growth rates in smart phones continue to flatten. In the past, it was a sure bet that pushing to the next process node would provide improvements in power, performance and cost. But after 22nm, the economics change due to the need for multi-patterning and finFETs, and th... » read more

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