The Automotive V-Cycle

By Ann Mutschler - 05 Nov, 2015 - Comments: 0

During the research for my article on making cars smarter, I learned from Andrew Patterson at [getentity id="22017" e_name="Mentor Graphics"] that when it comes to the [getkc id="10" kc_name="verification"] side, one well-established practice in the automotive industry is the use of the V-Cycle design methodology (also known as the V-Model) and that carmakers tend to follow that. He explain... » read more

The Cloud, The IoE, And You

By Ernest Worthman - 05 Nov, 2015 - Comments: 0

If you’re anywhere in the high-tech biz, the two terms that are rocking your world are the Internet of Everything and the Cloud. Whether you are on the inside track of these, or on the sidelines, they are going to be two of the most disruptive technologies of the 21st century. The cloud is already here and gaining momentum. Some people will argue that the cloud has been here since the ince... » read more

SoC Verification For The Internet of Things

By Mentor, a Siemens Business - 04 Nov, 2015 - Comments: 0

Larger, more complex designs with more software and tighter power budgets require new verification solutions that target the associated technological challenges. This paper explores why traditional digital simulation and hardware prototypes fall short when it comes to verifying IoT and network designs, why using emulation is critical for a total verification solution, and why traditional in-cir... » read more

Blog Review: Nov. 4

By Jesse Allen - 04 Nov, 2015 - Comments: 0

Can agile methodologies typically used in software development bring more efficiency to chip design? For UC Berkeley Professor Borivoje Nikolic, the answer is, why not? Christine Young reports on the keynote at Cadence's Mixed-Signal Technology Summit. For his latest embedded video, Mentor's Colin Walls focuses the camera on language standardization and use of language extensions. Ansys' ... » read more

The New Face of Formal

By Brian Bailey - 04 Nov, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager R&D, verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Normando... » read more

Making IP Secure

By Ann Mutschler - 02 Nov, 2015 - Comments: 0

[getkc id="43" comment="IP"] security is coming under increasing scrutiny as concerns about system and hardware security escalate. For IP, this is particularly critical because commercially available IP touches many players in the semiconductor and software ecosystem. IP users want to ensure they are using the IP as the provider intended and that they are protected against malicious code. IP... » read more

The Week In Review: Design/IoT

By Jesse Allen - 30 Oct, 2015 - Comments: 0

Tools Aldec introduced Hybrid Emulation including support for ARM Fast Models. Aldec says the capability to link an SoC emulation hardware platform with a virtual platform allows both software and hardware teams to work on the most up-to-date version of the project, long before first silicon is available, or even much of the RTL or IP has been completed. eSilicon's online quoting tools fo... » read more

HW Vs. SW: Who’s Leading Whom?

By Brian Bailey - 29 Oct, 2015 - Comments: 6

In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Hybrid Emulation Gets More Hybrid

By Ed Sperling - 29 Oct, 2015 - Comments: 0

Rising chip complexity is creating a booming emulation business, as chipmakers working at advanced nodes turn to bigger iron to get chips out the door on time. What started as a "shift lift"—doing more things earlier in the design cycle—is evolving into a more complex mix of hardware-accelerated verification for both hardware and software. There are even some new forays into power explor... » read more

Culture Clash In Analog

By Ann Mutschler - 29 Oct, 2015 - Comments: 2

The analog/mixed signal world is being shaken up by a mix of new tools, an influx of younger engineers with new and broader approaches, and an emphasis on changing methodologies to improve time to market. Analog and digital engineers have never quite seen eye-to-eye. Analog teams leverage techniques that have been around, in some cases, for decades, while digital teams rely heavily on the la... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?