Design Customization Puts Heavy Burden On Verification


Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor Engineering sat down with a panel of experts, including Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group director for verification software product management at Cad... » read more

Blog Review: Jan. 29


Cadence's Reela Samuel looks beyond silicon to new semiconductor materials under development and the particular applications for gallium nitride, silicon carbide, indium phosphide, glass, and diamond. Siemens' Kyle Fraunfelter and Melville Bryant find that lean approaches alone cannot address the increasingly complex sustainability challenges of semiconductor manufacturing and call for the e... » read more

Assembly Design Rules Slowly Emerge


Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Chip Industry Week In Review


The new Trump administration was quick to put a different stamp on the tech world: President Trump rescinded a long list of Biden’s executive orders, including those aimed at AI safety and the mandate for 50% EVs by 2030. Roughly 1.3 million EVs were sold in the U.S. in 2024, up 7.3% from 2023. The new administration announced $500 billion ($100 billion initially) in private sector in... » read more

Blog Review: Jan. 22


Cadence's David Shin provides an overview of the eUSB2V2 specification, which scales up to 4.8Gbps of data rate and provides the flexibility to configure either asymmetrical or symmetrical links depending on the intended application. Siemens EDA's Spencer Acain highlights the key role of AI in semiconductor testing, including the addition of analytical AI in DFT tools and how applying machin... » read more

Chip Industry Week In Review


GlobalFoundries will create a new center for advanced packaging and testing of U.S.-made essential chips within its New York manufacturing facility. A flurry of announcements on advanced semiconductors and AI rolled out this week as U.S. President Biden wrapped up his term: The Biden-Harris Administration released an Interim Final Rule on Artificial Intelligence Diffusion to strengthen ... » read more

Power Budgets Optimized By Managing Glitch Power


“Waste not, want not,” says the old adage, and in general, that’s good advice to live by. But in the realm of chip design, wasting power is a fact of physics. Glitch power – power that gets expended due to delays in gates and/or wires – can account for up to 40% of the power budget in advanced applications like data center servers. Even in less high-powered circuits, such as those fou... » read more

Tame IR Drop Like Google


In the relentless pursuit of semiconductor performance and efficiency, tech giants like Google are constantly pushing the boundaries of what's possible. As they scale their designs to the cutting-edge 3nm node, power integrity has emerged as a critical challenge that must be overcome. Enter Calibre DesignEnhancer (DE), Siemens' analysis-based solution for enhancing design reliability and man... » read more

What’s The Best Way To Sell An Inference Engine?


The burgeoning AI market has seen innumerable startups funded on the strength of their ideas about building faster, lower-power, and/or lower-cost AI inference engines. Part of the go-to-market dynamic has involved deciding whether to offer a chip or IP — with some newcomers pivoting between chip and IP implementations of their ideas. The fact that some companies choose to sell chips while... » read more

How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability


In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing p... » read more

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