The Power Of Shift-Left DRC Verification With Calibre nmDRC Recon


As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design


As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts. Foundry rules, shrinking geometries and advanced patterning have increased both the engineering effort and computational overhead needed for verification. Today, DRC isn’t just about sign-off—it�... » read more

Programmable Chips Evolve For Shifting Needs


ICs and SoCs are utilizing a range of processing elements that allow them to optimize current workloads while hedging their bets for the future. What used to be a simple choice between an ASIC, FPGA, or DSP, has evolved into a mix of processor types and architectures, including varying levels of programmability and customization. Speed is essential, but technology is evolving so quickly that... » read more

Chip Industry Week in Review


Government funding/defunding NIST is terminating funding for the SMART USA Institute, a CHIPS Act research center focused on digital twins, prompting congressional concern that the decision disrupts active awards and weakens U.S. semiconductor R&D commitments. Korea Zinc was awarded $210M in CHIPS Act funding towards a new $6.6B Tennessee advanced smelter and minerals processing facility,... » read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a... » read more

Blog Review: Dec. 17


Cadence's Shyam Sharma checks out what's new in the latest Open NAND Flash Interface 5.2 standard, including a Separate Command Address protocol that allows Hosts to optimize the command and data scheduling to increase overall available bandwidth. Siemens' Kyle Fraunfelter and Melville Bryant contend that improving semiconductor manufacturing and fab sustainability starts with a digital twin... » read more

Environmental Sensors Catch More Data For A Greener World


Sensors to detect temperature, pressure, and gases, such as CO2, have been around for centuries. However, the latest devices can measure a growing list of substances and process the data in real-time. Likewise, single-use sensors to measure pH levels in water are well established, but the latest water sensors can be deployed all along the pipeline from source to processing to outlet or tap, sav... » read more

Chip Industry Week in Review


Deals of the week: Arteris announced plans to acquire cybersecurity provider Cycuity. “Expanding our technology portfolio to include Cycuity’s hardware security assurance products will enable our customers to achieve secure on-chip data movement,” said Charlie Janac, chairman and CEO of Arteris. Qualcomm acquired Ventana Micro Systems, a maker of RISC-V data center-class CPU IP. ... » read more

AI Buildout Makes HPC Simulation More Challenging


Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

Evaluating A PDN Based On Jitter


Power distribution networks (PDN) must supply current fast enough to meet the switching needs of high-performance integrated circuits. As the voltage regulator module can only supply current up to a limited frequency range, decoupling capacitors are added to the PDN to provide a low impedance path for current to flow to the IC. This paper describes a simulation methodology to automatically meas... » read more

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