Chip Industry Week in Review

By The SE Staff - 09 Jan, 2026 - Comments: 0

SIA's latest monthly global semiconductor sales report reflects a ~30% YOY increase, hitting a record $75.3B in November 2025. Asia Pacific had a notable 66% increase. Cadence launched its Chiplet Spec-to-Packaged Parts ecosystem to accelerate time to market for chiplet development for physical AI, data centers, and HPC applications. Initial IP partners joining Cadence include Arm, Arteris, ... » read more

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL

By Vlada Kalinic - 08 Jan, 2026 - Comments: 0

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this code to RTL, which can be input to the traditional RTL downstream flow (RTL/GDS). Formally checking generated RTL can be difficult to analyze, as errors cannot be correlated to the HLS source code. ... » read more

Is End-To-End Security Possible?

By Ed Sperling - 08 Jan, 2026 - Comments: 0

Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Automotive Outlook: 2026

By Ann Mutschler - 08 Jan, 2026 - Comments: 0

The automotive industry stands at a crossroads entering 2026, facing a complex interplay of global tariffs, evolving electric vehicle (EV) dynamics, and the infusion of AI into just about everything. As manufacturers and suppliers navigate recent financing shifts and regulatory changes, they also must address consumer concerns over EV affordability and range, OEM concerns over when to develo... » read more

Formal Verification Of Synthesizable C++/SystemC Designs

By Siemens EDA - 07 Jan, 2026 - Comments: 0

Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL. High-level synthesis (HLS) is a design flow in which design intent is des... » read more

Blog Review: Jan. 7

By Jesse Allen - 07 Jan, 2026 - Comments: 0

Cadence's Reela Samuel presents an overview of through-silicon vias, including structure, pitch, and electrical behavior, key layout rules such as keep-out zones and stress constraints, and how TSV parasitics influence bandwidth, latency, and system-level performance. Siemens' Andras Vass-Varnai identifies five thermal trends to watch and how they’ll reshape design and packaging workflows ... » read more

Annual Global IC Fabs And Facilities Report

By Liz Allan - 07 Jan, 2026 - Comments: 0

Semiconductor companies announced a significant number of facilities in 2025 as global onshoring efforts continued across manufacturing, materials, packaging, design, and R&D. Investments came from both industry and government sources. Organizations worked together to solve current technology challenges, including soaring demand for AI chips and advanced memory, as well as complex applic... » read more

Chip Industry Week In Review

By The SE Staff - 29 Dec, 2025 - Comments: 0

Deals: NVIDIA inked a $20B non-exclusive licensing deal with Groq for its inference technology. The startup's founder, Jonathan Ross, and some other employees will join NVIDIA to assist in scaling and advancing the technology. The non-exclusive licensing deal, versus an outright purchase, is a tool other companies have used to avoid antitrust regulation. Samsung Ventures made a strategic inv... » read more

Blog Review: Dec. 24

By Jesse Allen - 24 Dec, 2025 - Comments: 0

Cadence's Jakob Engblom shares highlights from the recent SDV Europe conference, including why software-defined vehicles will require much closer, faster collaboration between suppliers and customers, with virtualization for software development and testing taking on a key role, as well as API questions and tire sensors. Synopsys' Tom De Schutter and Marc Serughetti predict that new cars wil... » read more

When To Move To Multi-Die Assemblies

By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

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