Streamlining DO-254 Compliance: The Power Of Automated Clock-Domain Crossing Verification


In the realm of safety-critical electronic hardware, particularly those governed by DO-254 compliance directives, ensuring design integrity is paramount. One of the most insidious challenges designers face is clock-domain crossing (CDC) violations. When data moves between asynchronous clock domains, it can lead to metastability issues, causing unpredictable behavior, data loss or corruption, an... » read more

Chiplets Vs. Soft IP: Different In Almost Every Way


Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different. Soft IP (also known as RTL IP) ... » read more

Adaptive Test Gaining Ground For HPC And AI Chips


Adaptive test is starting to gain traction for high-performance computing and AI chips as test programs that rely on static limits and fixed test sequences reach their practical limits. The growing complexity of multi-die assemblies and power delivery, along with increased stresses, are forcing a shift toward real-time, data-driven optimization at the test cell. “It’s the same old pro... » read more

Beyond The Core: Tackling System-Wide Debugging For Complex SoCs


The world of System-on-Chips (SoCs) is evolving – with the advancement of generative AI, the increasing demand for high-performance compute, and the innovative shift towards multi-chiplet architectures, system complexity is advancing at an increased pace. And with complexity comes an even greater challenge: debugging complexity. Silent data corruption, elusive timing-sensitive bugs, and i... » read more

DFT Shifts Further Left


Design for test is now an essential part of all advanced-node designs, but DFT dynamics are changing with the move to multi-die assemblies. More components, including chiplets, make it imperative to analyze more data earlier. Jeff Meyer, product manager for Tessent logic test at Siemens EDA, talks about how to reduce the cost of this analysis and the time it takes to do it, how much can be shif... » read more

Chip Industry Week in Review


Major Deals: Taiwan-based UMC is exploring possible collaboration with Polar Semiconductor for high-volume production of 8-inch wafers at Polar’s expanded Minnesota fab, a move that could provide domestic manufacturing capacity for automotive, data center, consumer, aerospace, and defense customers. Marvell will acquire Celestial AI for $3.25B, adding photonic fabric technology for o... » read more

Securing The Design Journey


In automotive, security, and pervasive computing, the stakes of failure have never been higher. Functional safety, security compliance, long product lifecycles, and system resilience are no longer differentiators — they are baseline requirements. Yet many semiconductor and system companies are still relying on an outdated engagement model built around static datasheets, fragmented tools, and ... » read more

Small Language Models Create New Security Risks


The rollout of edge AI is creating new security risks due to a mix of small language models (SLMs), their integration into increasingly complex hardware, and the behavior and interactions of both over time. AI data centers still garner the most attention due to massive investments and an ongoing flood of deals and acquisitions, but the edge is quietly starting to take shape for several reaso... » read more

Physical AI Takes Functional Safety Cues From Automotive


Robots are becoming smarter, more capable, and more pervasive, setting the stage for a whole new round of growth that will touch nearly every part of the semiconductor and software industries for decades to come. Robots are at the core of physical AI, a broad segment of edge AI systems that interact with the world through artificial intelligence and sensors. This includes everything from hum... » read more

Harnessing Silicon Lifecycle Management For Chip Security


Silicon lifecycle management is starting to be used in ways that extend well beyond its original mission of ensuring a chip functions to spec throughout its expected lifetime. While tracking aging effects and component failures are still important, the technology also is being deployed to proactively monitor, authenticate, and respond to potential threats in real-time. In fact, not applying ... » read more

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