Superconducting Material With Exceptional Tunability


A technical paper titled “Strain-switchable field-induced superconductivity” was published by researchers at Massachusetts Institute of Technology (MIT), University of Washington, Argonne National Laboratory, Cornell University, Zhejiang University of Science and Technology, and George Mason University. Abstract: "Field-induced superconductivity is a rare phenomenon where an applied magne... » read more

Research Bits: Jan. 2


Synaptic transistor Researchers from Northwestern University, Boston College, and MIT developed a synaptic transistor that simultaneously processes and stores information similar to the human brain. The team said the transistor goes beyond simple machine learning tasks to categorize data and is capable of performing associative learning. The new device is stable at room temperatures. It als... » read more

Research Bits: Dec. 18


Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Synopsys acquired Imperas, pushing further into the RISC-V world with Imperas' virtual platform technology for verifying and emulating processors. Synopsys has been building up its RISC-V portfolio, starting with ARC-V processor IP and a full suite of tools introduced last month. The first high-NA EUV R&D center in the U.S. will be built at... » read more

Chip Industry’s Technical Paper Roundup: Dec 11


New technical papers added to Semiconductor Engineering’s library this week. [table id=174 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Tapping 2D van der Waals Ferroelectrics For Use In Next-Generation Electronics


A technical paper titled “Domain-dependent strain and stacking in two-dimensional van der Waals ferroelectrics” was published by researchers at Rice University, Massachusetts Institute of Technology, University of Texas at Arlington, Texas A&M University, and Pennsylvania State University. Abstract: "Van der Waals (vdW) ferroelectrics have attracted significant attention for their pot... » read more

Chip Industry Week In Review


By Jesse Allen, Susan Rambo, and Liz Allan The U.S. government will invest about $3 billion for the National Advanced Packaging Manufacturing Program (NAPMP), including an advanced packaging piloting facility to help U.S. manufacturers adopt new technology and workforce training programs. It also will provide funding for projects concentrating on materials and substrates; equipment, tools, ... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, Jesse Allen, and Liz Allan President Biden issued an executive order on the “Safe, Secure, and Trustworthy Development and Use of Artificial Intelligence.” It says entities need to report large-scale computing clusters and the total computing power available, including “any model that was trained using a quantity of computing power greater than 1,026 inte... » read more

Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

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