Making Chips At 3nm And Beyond

By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Can Nano-Patterning Save Moore’s Law?

By Mark LaPedus - 19 Nov, 2015 - Comments: 0

For years the academic community has explored a novel technology called selective deposition. Then, more than a year ago, Intel spearheaded an effort to bring the technology from the lab to the fab at 7nm or 5nm. Today, selective deposition is still in R&D, but it is gaining momentum in the industry. With R&D funding from Intel and others, selective deposition, sometimes called ALD-e... » read more

New Patterning Paradigm?

By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chip scaling is becoming more difficult at each process node, but the industry continues to find new and innovative ways to solve the problems at every turn. And so chipmakers continue to march down the various process nodes. But the question is for how much longer? In fact, at 16nm/14nm and beyond, chipmakers are finding new and different challenges, which, in turn, could slow IC scaling or br... » read more

More Lithography Options?

By Mark LaPedus - 03 Mar, 2015 - Comments: 1

Lithographers face some tough decisions at 10nm and beyond. At these nodes, IC makers are still weighing the various patterning options. And to make it even more difficult, lithographers could soon have some new, and potentially disruptive, options on the table. On one front, the traditional next-generation lithography (NGL) technologies are finally making some noticeable progress. For examp... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: MLD

Making Chips At 3nm And Beyond

Can Nano-Patterning Save Moore’s Law?

New Patterning Paradigm?

More Lithography Options?