tag: modeling

Are Models Holding Back New Methodologies
By Brian Bailey - 23 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirmeister, group director,... » read more

Not Invented Here Syndrome
By Jon McDonald - 21 Aug, 2014 - Comments: 0

Recently I have made some choices on IP I needed to re-use and some I decided not to re-use. This got me thinking about the general topic of reuse in system-level design. Most will agree with a non-specific statement that reuse is a good thing, but the details tend to be a bit more ambiguous. Clouding the reuse question are occasional infections of NIH Syndrome (Not Invented Here), even if s... » read more

High-Level Gaps Emerge
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at Broadcom; Jon McDonald, technical marketing engineer at Mentor Graphics; Phil Bishop, vice president of the System Level Design System & Verification Group at Cadence; and Bernard Mu... » read more

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

Graphing Toward Standardization
By Brian Bailey - 24 Apr, 2014 - Comments: 0

Graph-based verification has become the hot topic of the day. It commanded a lot of attention at the recent DVCon, promises to fix many of the problems plaguing functional verification, can provide an automated way to perform system-level verification, enables portability of tests between simulation, emulation and prototyping, reduces the wastage created by constrained random test pattern gener... » read more

Abstractions: The Good, Bad And Ugly
By Ed Sperling - 27 Feb, 2014 - Comments: 0

Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Plans Vs. Planning
By Jon McDonald - 20 Dec, 2013 - Comments: 0

The end of the year is a good time to look back at what’s happened over the past year, and look ahead to what might happen in the coming one. Two quotes that help my thought process when thinking about the might be coming, “Change is the law of life.” from Kennedy, and “Plans are nothing, but planning is indispensable” from Eisenhower. From my perspective, 2013 has been a good year... » read more

Making Modeling Less Unpleasant
By Brian Bailey - 19 Dec, 2013 - Comments: 1

How many times did your mother tell you to take your medicine? You knew two things: a) it would be unpleasant and b) it would be worth the few seconds of unpleasantness because of the benefits it would provide. It appears as if the electronics industry has the same issue with modeling. We talk about the benefits that having a system-level model would have — the ability to explore system archi... » read more

A Nobel Prize For Modeling And Simulation
By Brian Bailey - 24 Oct, 2013 - Comments: 0

This year, a Nobel Prize has been awarded for devising a computer model and simulation process. Bloomberg, which interviewed Marinda Wu by phone, said: “The models let us slow down…and let us look at them one piece at a time.” This enables them to optimize things. At this point you may be thinking one of three things. Either 1) I don’t remember that prize being awarded or, 2) at last ED... » read more

Divide, Abstract And Conquer
By Ed Sperling - 03 May, 2013 - Comments: 0

For years, the motto among design and verification engineers has been to look at the individual pieces of a design because it’s impossible to have a single tool or even an integrated collection of tools that can debug everything. That approach isn’t changing, but the method for getting there is. The driver behind this shift is a familiar one—growing complexity. Even platforms and subsy... » read more

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