The Week In Review: Design

Mentor adds embedded Linux for AMD chips; Apache, TowerJazz roll out power noise and reliability signoff kit; Synopsys boosts formal and static tools; Accellera updates mixed signal standard; Intel gets serious about foundry services; ARM sets up design center in Taiwan; Aart plays the blues.

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Tools
Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs.

Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance.

Synopsys updated its verification portfolio with static and formal tools for CDC and low-power static checking. The company says the new tools improve performance by 3X to 5X.

IP
Synopsys introduced new memory verification IP for DDR4/3 and LPDDR4/3/2 to speed up SoC verification.  The company also introduced IP prototyping kits, software development kits and customized IP subsystems, which it is calling IP acceleration.

Standards
Accellera enhanced its mixed-signal modeling and verification in the new Verilog-AMS 2.4 standard, extending compact modeling and behavior modeling. The revised language reference manual is now available for download.

Deals
Synopsys is working with STMicroelectronics and Samsung to accelerate adoption of 28nm FD-SOI. Samsung is a latecomer to the FD-SOI party, but its support will go a long way toward making this a mainstream technology.

Cadence won a deal with On Semiconductor, which is using its layout suite for analyzing parasitics and electromigration.

Atrenta won a deal with Mediatek, which has adopted its design for test tool suite for its workflows.

Synopsys’ Coverity subsidiary won a deal with Sigma³, which is using the Coverity software test platform to improve the quality and security of its oil and gas exploration software.

ARM is setting up a design center in Taiwan focused on the Internet of Things and embedded device development. This is ARM’s first CPU design center in Asia.

Certifications
It appears that Intel is getting more serious about its foundry business. Cadence’s custom/analog tools,  Mentor’s suite of tools, and Synopsys’ tools and IP are now enabled for Intel’s 14nm Tri-gate design process.

Mentor also said its DFM decks for signoff verification will support both Samsung and GlobalFoundries 14nm finFET processes.

Benefit concert
Synopsys CEO Aart de Geus and his band, Legally Blue, will play a benefit concert in support of the Second Harvest Food Bank for children’s hunger at 5 p.m. on Saturday, June 14, in Santana Row, San Jose.