Creating Better Models For Software And Hardware Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Models Built With Water


A couple of years ago I wrote a post using the famous quote by statistician George Box: All Models Are Wrong; Some Are Useful. In that post, I discussed paper and plastic airplanes, but mostly I talked about modeling in computers, and especially what I call the "digital illusion." The digital illusion is the idea that signals in digital chips are ones and zeros, with timing, and not analog vol... » read more

Holes In AI Security


Mike Borza, principal security technologist in Synopsys’ Solutions Group, explains why security is lacking in AI, why AI is especially susceptible to Trojans, and why small changes in training data can have big impacts on many devices. » read more

Defining Verification


There was a time when the notion of rigorous verification was seen as being unnecessary and even wasteful. I can remember early in my career working on flight control computers. We did no functional verification and created no models. We prototyped it and ran some engineering tests through it, primarily to structurally verify the system. We did not test the functionality of the system – that ... » read more

Finding Code Problems Before High-Level Synthesis


In order to significantly speed up verification and to handle complex algorithms that change daily, many companies are turning to a High-Level Synthesis (HLS) methodology. But, it is extremely important that the high-level C++ model is correct. In addition, the C++ language has ambiguities that can be tough to catch during simulation. Even if correctly written, the high-level model could be cod... » read more

The Value Of A Model


Increased talk about the Digital Twin has brought models to the forefront of the discussion. What are the right models for particular applications? What is the correct level of abstraction? Where do the models come from and how are they maintained? How does one value a model? The semiconductor industry has been reluctant to create any model that is not directly used in the development path. ... » read more

So Many Waivers Hiding Issues


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Autonomy, Electrification And The Rise Of Model-Based EE Design


Powerful software that automatically transforms input models into deterministic outputs is transforming automotive electrical and electronics (EE) design. Martin O'Brien and Dan Scott set the stage for Mentor's advanced generative engineering approach. To read more, click here. » read more

Comprehensive CDC Verification Using Advanced Hierarchical Data Models


In this paper, we describe the hierarchical data model (HDM), which is a performance efficient alternative to the traditional flat CDC verification flow. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly re-used across releases and across designs wherever the IP i... » read more

The Veloce Strato Platform: Unique Core Components Create High-Value Advantages


The Veloce Strato Emulation platform has sufficient execution speed, full visibility capabilities and ease-of-use in model creation and model updates to span the entire range of needs throughout the life of the design development process. To read more, click here. » read more

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