Why Use A Package?

By Ed Sperling - 21 Jan, 2016 - Comments: 0

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department—and a former fellow and director of the systems scaling technology department at IBM—sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation. SE: Advanced packaging is being viewed as a way to extend scaling in the fut... » read more

The Internet Of Power Also Benefits From Moore’s Law

By Imec - 21 Jan, 2016 - Comments: 0

By Jef Poortmans It may sound strange, but striving to achieve smaller dimensions with Moore’s Law is an important enabler for producing increasingly better solar cells, with a more elaborate technology toolbox (including ALD, epitaxy, etc.) Improved process steps are constantly being developed to achieve these small transistor dimensions (for growing material layers or to etch away str... » read more

Predictions For 2016: Semiconductors, Manufacturing And Design

By Brian Bailey - 21 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Will 5nm Happen?

By Mark LaPedus - 20 Jan, 2016 - Comments: 7

Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017. So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few compani... » read more

Thinking Outside The Chip

By Ed Sperling - 14 Jan, 2016 - Comments: 0

Intel will begin adding 2.5D and 3D packaging into its processors, following the lead set by IBM and AMD in recognizing that new packaging approaches are essential for improving performance and lowering power. This shift won't derail the semiconductor industry's efforts to the reach future process nodes or continually shrink features, but it does add context for other factors that in... » read more

Shifting Performance Bottlenecks Driving Change In Chip And System Architectures

By Steven Woo - 14 Jan, 2016 - Comments: 0

The rise of personal computing in the 1980s — along with graphical user interfaces (GUIs) and applications ranging from office apps to databases — drove the demand for faster chips capable of removing processing bottlenecks and delivering a more responsive end-user experience. Indeed, the semiconductor industry has certainly come quite a long way since IBM launched its PC way back in 1981. ... » read more

Executive Insight: Sehat Sutardja

By Ed Sperling - 11 Jan, 2016 - Comments: 1

Sehat Sutardja, chairman and CEO of Marvell, sat down with Semiconductor Engineering to talk about new approaches for design and memory and why costs and time to market are forcing changes in Moore's Law. What follows are excerpts of that conversation. SE: What was behind your move into modular packaging? Sutardja: The cost of building chips is getting out of hand. As we make things more ... » read more

Changes In Chip Design

By Ernest Worthman - 07 Jan, 2016 - Comments: 0

We all know that sub-10nm is coming. But is that really what will define the next generation of semiconductors? Progress in semiconductor technology increasingly is not just about advancements in the hardware. It also involves advancements in applications and technologies peripheral to the devices themselves. That may sound counterintuitive, but going forward the technology, applications and... » read more

Behind The Intel-Altera Deal

By Ed Sperling - 31 Dec, 2015 - Comments: 3

Intel completed its $16.7 billion acquisition of Altera this week, wrapping up what is arguably the semiconductor industry's most important M&A transaction of 2015. Time and numbers will tell exactly how important. There are two big challenges to making this deal work. One involves a big shift in direction away from simply shrinking features to include new architectures and packaging approac... » read more

The Biggest Stories

By Ed Sperling - 22 Dec, 2015 - Comments: 0

As tech journalists we are devout interpreters and re-interpreters of our own statistics. We can track how many clicks a story gets, which region or country those clicks come from, and how much interest there is in various subjects over time. The publishing industry always has been driven by data. In the early part of the 20th century, newspapers were engaged in circulation battles, which we... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: Moore’s Law