5 Things To Know About The IoT

By Ed Sperling - 06 Aug, 2015 - Comments: 0

The IoT means many things to many people. While the numbers and projections are all very large, the views of what it actually means are vastly different because it can include anything from a sensor in a car or an ingestible medical device to a data center full of servers and the connectivity in between. But there are some interesting shifts under way, both driving the [getkc id="76" comment... » read more

The Future Of Moore’s Law

By Ed Sperling - 03 Aug, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at [getentity id="22819" comment="GlobalFoundries"]; Charlie Cheng, CEO of [getentity id="2... » read more

Which Process, Material, IP?

By Ed Sperling - 30 Jul, 2015 - Comments: 1

For years chipmakers have been demanding more choices. They've finally gotten what they wished for—so many possibilities, in fact, that engineering teams of all types are having trouble wading through them. And to make matters worse, some choices now come with unexpected and often unwanted caveats. At the most advanced nodes it's a given that being able to shrink features and double patter... » read more

Technology Tsunami Approaches

By Brian Bailey - 27 Jul, 2015 - Comments: 0

How many times have we heard the saying that technology advancements are accelerating and that inevitably the older generation will have increasing problems keeping up with the new advancements? This happened to me with software development methodologies over fifteen years ago. I still program, when people actually let me, using basically the same techniques I learned when I was in my teens.... » read more

The Future Of Moore’s Law

By Ed Sperling - 22 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Charlie Cheng, CEO of [getentity id="22135" e_name="Kilopass Technology"... » read more

Power Breaks Everything

By Ed Sperling - 15 Jul, 2015 - Comments: 2

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Tech Talk: 22nm FD-SOI

By Ed Sperling - 13 Jul, 2015 - Comments: 0

Subramani Kengeri, vice president of global design solutions at GlobalFoundries, discusses the evolution of 22nm FD-SOI and its advantages, including single patterning in the middle end of line, 0.4 volt operating voltage, and how it compares to finFETs in terms of performance. [youtube vid=5fa1AcIGcUw] » read more

Moore’s Law Reset?

By Ed Sperling - 13 Jul, 2015 - Comments: 0

GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

Here Comes 7nm

By Ed Sperling - 09 Jul, 2015 - Comments: 0

A consortium of companies involving IBM, GlobalFoundries and Samsung has rolled out the first 7nm test chip using silicon germanium as a substrate, using EUV to pattern multiple layers. While this doesn't mean the cost equation is even close to being solved, or that more than a handful of companies will push forward to that node anytime soon using SiGe as the substrate material, it does cre... » read more

Moore Memory Problems

By Brian Bailey - 09 Jul, 2015 - Comments: 0

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: Moore’s Law

5 Things To Know About The IoT

The Future Of Moore’s Law

Which Process, Material, IP?

Technology Tsunami Approaches

The Future Of Moore’s Law

Power Breaks Everything

Tech Talk: 22nm FD-SOI

Moore’s Law Reset?

Here Comes 7nm

Moore Memory Problems