Moving Electrons Is Getting Harder

After years of progress in semiconductor design, it might be time to rethink the path forward…and clarify the numbers used along the way.


Numerous executives across the ecosystem—from EDA and equipment companies to foundries—recently have stated that Moore’s Law has at least 10 more years of life. This is interesting math, considering the semiconductor industry is now working on 10nm, with chips expected to roll out next year.

So given that Moore’s Law is on a two-year cadence of doubling the number of transistors every 24 months, and assuming we’re almost to 10nm, in a decade we should be churning out chips at 1.5nm or whatever the actual number is (10,7,5,3,1.5). It might be possible to get there, and there are brilliant and determined scientists working in this industry who have defied theoretical limits on multiple occasions. But the probability is growing that some entirely new paths will be required. Continuing to push electrons through increasingly smaller wires will meet more resistance, which in turn will generate enough heat to melt those wires and the devices around them.

Early research shows that at 5nm quantum effects become much more problematic. Rather than smoothly moving between wires and in and out of memory, electrons will move much more erratically. This is why there has been so much research lately into new materials. This is new territory for everyone except theoretical physicists. Most of the work so far has been on physical effects rather than quantum effects, and while the manifestation of both may be the same, the impact on heat, power consumption and performance is unknown.

This may be a great time to begin mapping the laws of the universe and the bending of space and time, but it raises serious questions about shrinking features. At 16/14nm, thermal issues already are a big issue. At 10nm, thermal coupling becomes a design worry, regardless of the structure of the transistor, whether it’s based on carbon nanotubes or gate-all-around nanowires or some other exotic combination. At 5nm, no one knows what to expect or how to route the heat caused by increased dynamic power out of densely packed planar devices.

There are options, of course. The end is not near, although the solution might be radically different. Moving signals with photonics is one of them. Photons generate less heat than electrons, although they’re more difficult to control in ad hoc interactions of different functions on a device. Slimming designs down into platforms that can be stacked, either vertically or horizontally, is another option—and one that is gaining ground. Staying at existing nodes by using new materials such as FD-SOI or SiGe is another. And making cycles much more efficient through hardware-software co-design and more emphasis on parallel processing is yet another.

The key metrics of power, notably longer battery life or lower data center costs, as well as the cost of designing and implementing chips, still apply. And while performance is less of a critical issue in some cases—the current rule of thumb is that it can’t decrease—in some new applications it actually has to increase. Think of a backup camera on a car, for example. It has to start up faster and do more than ever before.

Not all of this needs to happen at 3nm, though. And as questions continue to mount about the path forward and what’s next, Semiconductor Engineering asked how these executives justify their projection of at least 10 more years. Their answer is that the bulk of the industry is actually at 28nm, and only the bleeding edge is at 16/14nm. Translation: The starting line for the next nodes is now as hazy as the leading edge, and if you thought it was confusing before, wait until we really do get to 5nm when even the behavior of electrons is confusing, erratic and they become much, much harder to push around.


Kev says:

Measurements sub 28nm are a bit bogus, they should really be giving a gate-density number – the 3nm isn’t the channel length.

Density-wise current Silicon has an active layer that isn’t very thick, and at least one company can do ICs that are only 10um. So the opportunity to go 3D and really ramp up the functional density is definitely there. However, that requires Silicon to be largely “dark” through sub-threshold operation and/or asynchronous design so it doesn’t melt.

(IMO) Moore’s Law will continue by use of 3D/stacking in the short term, but scaling will be back in a few years after EUV fails and the money goes into something else.

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